[raggedstone] / dhwk / source / top.vhd

-- VHDL model created from schematic top.sch -- Jan 09 20:54:18 2007\r
\r
\r
\r
LIBRARY ieee;\r
\r
USE ieee.std_logic_1164.ALL;\r
USE ieee.numeric_std.ALL;\r
\r
\r
entity dhwk is\r
      Port ( KONST_1 : In    std_logic;\r
             PCI_CBEn : In    std_logic_vector (3 downto 0);\r
             PCI_CLOCK : In    std_logic;\r
             PCI_FRAMEn : In    std_logic;\r
             PCI_IDSEL : In    std_logic;\r
             PCI_IRDYn : In    std_logic;\r
             PCI_RSTn : In    std_logic;\r
--             SERIAL_IN : In    std_logic;\r
--             SPC_RDY_IN : In    std_logic;\r
             TAST_RESn : In    std_logic;\r
             TAST_SETn : In    std_logic;\r
              PCI_AD : InOut std_logic_vector (31 downto 0);\r
             PCI_PAR : InOut std_logic;\r
             PCI_DEVSELn : Out   std_logic;\r
             PCI_INTAn : Out   std_logic;\r
             PCI_PERRn : Out   std_logic;\r
             PCI_SERRn : Out   std_logic;\r
             PCI_STOPn : Out   std_logic;\r
             PCI_TRDYn : Out   std_logic;\r
--             SERIAL_OUT : Out   std_logic;\r
--             SPC_RDY_OUT : Out   std_logic;\r
             TB_IDSEL : Out   std_logic;\r
             TB_nDEVSEL : Out   std_logic;\r
             TB_nINTA : Out   std_logic );\r
end dhwk;\r
\r
architecture SCHEMATIC of dhwk is\r
\r
   SIGNAL gnd : std_logic := '0';\r
   SIGNAL vcc : std_logic := '1';\r
\r
   signal READ_XX7_6 : std_logic;\r
   signal  RESERVE : std_logic;\r
   signal SR_ERROR : std_logic;\r
   signal  R_ERROR : std_logic;\r
   signal  S_ERROR : std_logic;\r
   signal WRITE_XX3_2 : std_logic;\r
   signal WRITE_XX5_4 : std_logic;\r
   signal WRITE_XX7_6 : std_logic;\r
   signal READ_XX1_0 : std_logic;\r
   signal READ_XX3_2 : std_logic;\r
   signal    INTAn : std_logic;\r
   signal    TRDYn : std_logic;\r
   signal READ_XX5_4 : std_logic;\r
   signal  DEVSELn : std_logic;\r
   signal FIFO_RDn : std_logic;\r
   signal WRITE_XX1_0 : std_logic;\r
   signal REG_OUT_XX6 : std_logic_vector (7 downto 0);\r
   signal SYNC_FLAG : std_logic_vector (7 downto 0);\r
   signal  INT_REG : std_logic_vector (7 downto 0);\r
   signal REVISON_ID : std_logic_vector (7 downto 0);\r
   signal VENDOR_ID : std_logic_vector (15 downto 0);\r
   signal READ_SEL : std_logic_vector (1 downto 0);\r
   signal   AD_REG : std_logic_vector (31 downto 0);\r
   signal REG_OUT_XX7 : std_logic_vector (7 downto 0);\r
   signal R_EFn : std_logic;\r
   signal R_FFn : std_logic;\r
   signal R_FIFO_Q_OUT : std_logic_vector (7 downto 0);\r
   signal R_HFn : std_logic;\r
   signal S_EFn : std_logic;\r
   signal S_FFn : std_logic;\r
   signal S_FIFO_Q_OUT : std_logic_vector (7 downto 0);\r
   signal S_HFn : std_logic;\r
   signal R_FIFO_D_IN : std_logic_vector (7 downto 0);\r
   signal R_FIFO_READn : std_logic;\r
   signal R_FIFO_RESETn : std_logic;\r
   signal R_FIFO_RTn : std_logic;\r
   signal R_FIFO_WRITEn : std_logic;\r
   signal S_FIFO_D_IN : std_logic_vector (7 downto 0);\r
   signal S_FIFO_READn : std_logic;\r
   signal S_FIFO_RESETn : std_logic;\r
   signal S_FIFO_RTn : std_logic;\r
   signal S_FIFO_WRITEn : std_logic;\r
   signal SERIAL_IN : std_logic;\r
   signal SPC_RDY_IN : std_logic;\r
   signal SERIAL_OUT : std_logic;\r
   signal SPC_RDY_OUT : std_logic;\r
\r
   component MESS_1_TB\r
      Port ( DEVSELn : In    std_logic;\r
               INTAn : In    std_logic;\r
             KONST_1 : In    std_logic;\r
             PCI_IDSEL : In    std_logic;\r
             REG_OUT_XX7 : In    std_logic_vector (7 downto 0);\r
             TB_DEVSELn : Out   std_logic;\r
             TB_INTAn : Out   std_logic;\r
             TB_PCI_IDSEL : Out   std_logic );\r
   end component;\r
\r
   component VEN_REV_ID\r
      Port (  REV_ID : Out   std_logic_vector (7 downto 0);\r
              VEN_ID : Out   std_logic_vector (15 downto 0) );\r
   end component;\r
\r
   component INTERRUPT\r
      Port ( INT_IN_0 : In    std_logic;\r
             INT_IN_1 : In    std_logic;\r
             INT_IN_2 : In    std_logic;\r
             INT_IN_3 : In    std_logic;\r
             INT_IN_4 : In    std_logic;\r
             INT_IN_5 : In    std_logic;\r
             INT_IN_6 : In    std_logic;\r
             INT_IN_7 : In    std_logic;\r
             INT_MASKE : In    std_logic_vector (7 downto 0);\r
             INT_RES : In    std_logic_vector (7 downto 0);\r
             PCI_CLOCK : In    std_logic;\r
             PCI_RSTn : In    std_logic;\r
             READ_XX5_4 : In    std_logic;\r
               RESET : In    std_logic;\r
             TAST_RESn : In    std_logic;\r
             TAST_SETn : In    std_logic;\r
               TRDYn : In    std_logic;\r
             INT_REG : Out   std_logic_vector (7 downto 0);\r
               INTAn : Out   std_logic;\r
             PCI_INTAn : Out   std_logic );\r
   end component;\r
\r
   component FIFO_CONTROL\r
      Port ( FIFO_RDn : In    std_logic;\r
             FLAG_IN_0 : In    std_logic;\r
             FLAG_IN_4 : In    std_logic;\r
                HOLD : In    std_logic;\r
             KONST_1 : In    std_logic;\r
             PCI_CLOCK : In    std_logic;\r
             PSC_ENABLE : In    std_logic;\r
               R_EFn : In    std_logic;\r
               R_FFn : In    std_logic;\r
               R_HFn : In    std_logic;\r
               RESET : In    std_logic;\r
               S_EFn : In    std_logic;\r
               S_FFn : In    std_logic;\r
             S_FIFO_Q_OUT : In    std_logic_vector (7 downto 0);\r
               S_HFn : In    std_logic;\r
             SERIAL_IN : In    std_logic;\r
             SPC_ENABLE : In    std_logic;\r
             SPC_RDY_IN : In    std_logic;\r
             WRITE_XX1_0 : In    std_logic;\r
             R_ERROR : Out   std_logic;\r
             R_FIFO_D_IN : Out   std_logic_vector (7 downto 0);\r
             R_FIFO_READn : Out   std_logic;\r
             R_FIFO_RESETn : Out   std_logic;\r
             R_FIFO_RETRANSMITn : Out   std_logic;\r
             R_FIFO_WRITEn : Out   std_logic;\r
             RESERVE : Out   std_logic;\r
             S_ERROR : Out   std_logic;\r
             S_FIFO_READn : Out   std_logic;\r
             S_FIFO_RESETn : Out   std_logic;\r
             S_FIFO_RETRANSMITn : Out   std_logic;\r
             S_FIFO_WRITEn : Out   std_logic;\r
             SERIAL_OUT : Out   std_logic;\r
             SPC_RDY_OUT : Out   std_logic;\r
             SR_ERROR : Out   std_logic;\r
             SYNC_FLAG : Out   std_logic_vector (7 downto 0) );\r
   end component;\r
\r
   component PCI_TOP\r
      Port (    FLAG : In    std_logic_vector (7 downto 0);\r
             INT_REG : In    std_logic_vector (7 downto 0);\r
             PCI_CBEn : In    std_logic_vector (3 downto 0);\r
             PCI_CLOCK : In    std_logic;\r
             PCI_FRAMEn : In    std_logic;\r
             PCI_IDSEL : In    std_logic;\r
             PCI_IRDYn : In    std_logic;\r
             PCI_RSTn : In    std_logic;\r
             R_FIFO_Q : In    std_logic_vector (7 downto 0);\r
             REVISON_ID : In    std_logic_vector (7 downto 0);\r
             VENDOR_ID : In    std_logic_vector (15 downto 0);\r
              PCI_AD : InOut std_logic_vector (31 downto 0);\r
             PCI_PAR : InOut std_logic;\r
              AD_REG : Out   std_logic_vector (31 downto 0);\r
             DEVSELn : Out   std_logic;\r
             FIFO_RDn : Out   std_logic;\r
             PCI_DEVSELn : Out   std_logic;\r
             PCI_PERRn : Out   std_logic;\r
             PCI_SERRn : Out   std_logic;\r
             PCI_STOPn : Out   std_logic;\r
             PCI_TRDYn : Out   std_logic;\r
             READ_SEL : Out   std_logic_vector (1 downto 0);\r
             READ_XX1_0 : Out   std_logic;\r
             READ_XX3_2 : Out   std_logic;\r
             READ_XX5_4 : Out   std_logic;\r
             READ_XX7_6 : Out   std_logic;\r
             REG_OUT_XX0 : Out   std_logic_vector (7 downto 0);\r
             REG_OUT_XX6 : Out   std_logic_vector (7 downto 0);\r
             REG_OUT_XX7 : Out   std_logic_vector (7 downto 0);\r
               TRDYn : Out   std_logic;\r
             WRITE_XX1_0 : Out   std_logic;\r
             WRITE_XX3_2 : Out   std_logic;\r
             WRITE_XX5_4 : Out   std_logic;\r
             WRITE_XX7_6 : Out   std_logic );\r
   end component;\r
\r
component fifo_generator_v3_2\r
        port (\r
        clk: IN std_logic;\r
        din: IN std_logic_VECTOR(7 downto 0);\r
        rd_en: IN std_logic;\r
        rst: IN std_logic;\r
        wr_en: IN std_logic;\r
        almost_empty: OUT std_logic;\r
        almost_full: OUT std_logic;\r
        dout: OUT std_logic_VECTOR(7 downto 0);\r
        empty: OUT std_logic;\r
        full: OUT std_logic;\r
        prog_full: OUT std_logic);\r
end component;\r
\r
begin\r
	SERIAL_IN <= SERIAL_OUT;\r
	SPC_RDY_IN <= SPC_RDY_OUT;\r
\r
   I19 : MESS_1_TB\r
      Port Map ( DEVSELn=>DEVSELn, INTAn=>INTAn, KONST_1=>KONST_1,\r
                 PCI_IDSEL=>PCI_IDSEL,\r
                 REG_OUT_XX7(7 downto 0)=>REG_OUT_XX7(7 downto 0),\r
                 TB_DEVSELn=>TB_nDEVSEL, TB_INTAn=>TB_nINTA,\r
                 TB_PCI_IDSEL=>TB_IDSEL );\r
   I18 : VEN_REV_ID\r
      Port Map ( REV_ID(7 downto 0)=>REVISON_ID(7 downto 0),\r
                 VEN_ID(15 downto 0)=>VENDOR_ID(15 downto 0) );\r
   I16 : INTERRUPT\r
      Port Map ( INT_IN_0=>SYNC_FLAG(1), INT_IN_1=>SYNC_FLAG(6),\r
                 INT_IN_2=>KONST_1, INT_IN_3=>KONST_1, INT_IN_4=>KONST_1,\r
                 INT_IN_5=>KONST_1, INT_IN_6=>KONST_1, INT_IN_7=>KONST_1,\r
                 INT_MASKE(7 downto 0)=>REG_OUT_XX6(7 downto 0),\r
                 INT_RES(7 downto 0)=>AD_REG(7 downto 0),\r
                 PCI_CLOCK=>PCI_CLOCK, PCI_RSTn=>PCI_RSTn,\r
                 READ_XX5_4=>READ_XX5_4, RESET=>REG_OUT_XX7(0),\r
                 TAST_RESn=>TAST_RESn, TAST_SETn=>TAST_SETn,\r
                 TRDYn=>TRDYn, INT_REG(7 downto 0)=>INT_REG(7 downto 0),\r
                 INTAn=>INTAn, PCI_INTAn=>PCI_INTAn );\r
   I14 : FIFO_CONTROL\r
      Port Map ( FIFO_RDn=>FIFO_RDn, FLAG_IN_0=>R_ERROR,\r
                 FLAG_IN_4=>S_ERROR, HOLD=>READ_SEL(0), KONST_1=>KONST_1,\r
                 PCI_CLOCK=>PCI_CLOCK, PSC_ENABLE=>REG_OUT_XX7(1),\r
                 R_EFn=>R_EFn, R_FFn=>R_FFn, R_HFn=>R_HFn,\r
                 RESET=>REG_OUT_XX7(0), S_EFn=>S_EFn, S_FFn=>S_FFn,\r
                 S_FIFO_Q_OUT(7 downto 0)=>S_FIFO_Q_OUT(7 downto 0),\r
                 S_HFn=>S_HFn, SERIAL_IN=>SERIAL_IN,\r
                 SPC_ENABLE=>REG_OUT_XX7(2), SPC_RDY_IN=>SPC_RDY_IN,\r
                 WRITE_XX1_0=>WRITE_XX1_0, R_ERROR=>R_ERROR,\r
                 R_FIFO_D_IN(7 downto 0)=>R_FIFO_D_IN(7 downto 0),\r
                 R_FIFO_READn=>R_FIFO_READn,\r
                 R_FIFO_RESETn=>R_FIFO_RESETn,\r
                 R_FIFO_RETRANSMITn=>R_FIFO_RTn,\r
                 R_FIFO_WRITEn=>R_FIFO_WRITEn, RESERVE=>RESERVE,\r
                 S_ERROR=>S_ERROR, S_FIFO_READn=>S_FIFO_READn,\r
                 S_FIFO_RESETn=>S_FIFO_RESETn,\r
                 S_FIFO_RETRANSMITn=>S_FIFO_RTn,\r
                 S_FIFO_WRITEn=>S_FIFO_WRITEn, SERIAL_OUT=>SERIAL_OUT,\r
                 SPC_RDY_OUT=>SPC_RDY_OUT, SR_ERROR=>SR_ERROR,\r
                 SYNC_FLAG(7 downto 0)=>SYNC_FLAG(7 downto 0) );\r
   I1 : PCI_TOP\r
      Port Map ( FLAG(7 downto 0)=>SYNC_FLAG(7 downto 0),\r
                 INT_REG(7 downto 0)=>INT_REG(7 downto 0),\r
                 PCI_CBEn(3 downto 0)=>PCI_CBEn(3 downto 0),\r
                 PCI_CLOCK=>PCI_CLOCK, PCI_FRAMEn=>PCI_FRAMEn,\r
                 PCI_IDSEL=>PCI_IDSEL, PCI_IRDYn=>PCI_IRDYn,\r
                 PCI_RSTn=>PCI_RSTn,\r
                 R_FIFO_Q(7 downto 0)=>R_FIFO_Q_OUT(7 downto 0),\r
                 REVISON_ID(7 downto 0)=>REVISON_ID(7 downto 0),\r
                 VENDOR_ID(15 downto 0)=>VENDOR_ID(15 downto 0),\r
                 PCI_AD(31 downto 0)=>PCI_AD(31 downto 0),\r
                 PCI_PAR=>PCI_PAR,\r
                 AD_REG(31 downto 0)=>AD_REG(31 downto 0),\r
                 DEVSELn=>DEVSELn, FIFO_RDn=>FIFO_RDn,\r
                 PCI_DEVSELn=>PCI_DEVSELn, PCI_PERRn=>PCI_PERRn,\r
                 PCI_SERRn=>PCI_SERRn, PCI_STOPn=>PCI_STOPn,\r
                 PCI_TRDYn=>PCI_TRDYn,\r
                 READ_SEL(1 downto 0)=>READ_SEL(1 downto 0),\r
                 READ_XX1_0=>READ_XX1_0, READ_XX3_2=>READ_XX3_2,\r
                 READ_XX5_4=>READ_XX5_4, READ_XX7_6=>READ_XX7_6,\r
                 REG_OUT_XX0(7 downto 0)=>S_FIFO_D_IN(7 downto 0),\r
                 REG_OUT_XX6(7 downto 0)=>REG_OUT_XX6(7 downto 0),\r
                 REG_OUT_XX7(7 downto 0)=>REG_OUT_XX7(7 downto 0),\r
                 TRDYn=>TRDYn, WRITE_XX1_0=>WRITE_XX1_0,\r
                 WRITE_XX3_2=>WRITE_XX3_2, WRITE_XX5_4=>WRITE_XX5_4,\r
                 WRITE_XX7_6=>WRITE_XX7_6 );\r
\r
receive_fifo : fifo_generator_v3_2\r
                port map (\r
                        clk => PCI_CLOCK,\r
                        din => R_FIFO_D_IN,\r
                        rd_en => not R_FIFO_READn,\r
                        rst => not R_FIFO_RESETn,\r
                        wr_en => not R_FIFO_WRITEn,\r
                        dout => R_FIFO_Q_OUT,\r
                        empty => R_EFn,\r
                        full => R_FFn,\r
                        prog_full => R_HFn);\r
\r
send_fifo : fifo_generator_v3_2\r
                port map (\r
                        clk => PCI_CLOCK,\r
                        din => S_FIFO_D_IN,\r
                        rd_en => not S_FIFO_READn,\r
                        rst => not S_FIFO_RESETn,\r
                        wr_en => not S_FIFO_WRITEn,\r
                        dout => S_FIFO_Q_OUT,\r
                        empty => S_EFn,\r
                        full => S_FFn,\r
                        prog_full => S_HFn);\r
end SCHEMATIC;\r
Commit	Line	Data
377c0242	1	-- VHDL model created from schematic top.sch -- Jan 09 20:54:18 2007\r
	2	\r
	3	\r
	4	\r
	5	LIBRARY ieee;\r
	6	\r
	7	USE ieee.std_logic_1164.ALL;\r
	8	USE ieee.numeric_std.ALL;\r
	9	\r
	10	\r
62946980	11	entity dhwk is\r
377c0242	12	Port ( KONST_1 : In std_logic;\r
	13	PCI_CBEn : In std_logic_vector (3 downto 0);\r
	14	PCI_CLOCK : In std_logic;\r
	15	PCI_FRAMEn : In std_logic;\r
	16	PCI_IDSEL : In std_logic;\r
	17	PCI_IRDYn : In std_logic;\r
	18	PCI_RSTn : In std_logic;\r
257c0fc1	19	-- SERIAL_IN : In std_logic;\r
257c0fc1	20	-- SPC_RDY_IN : In std_logic;\r
377c0242	21	TAST_RESn : In std_logic;\r
	22	TAST_SETn : In std_logic;\r
	23	PCI_AD : InOut std_logic_vector (31 downto 0);\r
	24	PCI_PAR : InOut std_logic;\r
	25	PCI_DEVSELn : Out std_logic;\r
	26	PCI_INTAn : Out std_logic;\r
	27	PCI_PERRn : Out std_logic;\r
	28	PCI_SERRn : Out std_logic;\r
	29	PCI_STOPn : Out std_logic;\r
	30	PCI_TRDYn : Out std_logic;\r
257c0fc1	31	-- SERIAL_OUT : Out std_logic;\r
257c0fc1	32	-- SPC_RDY_OUT : Out std_logic;\r
377c0242	33	TB_IDSEL : Out std_logic;\r
	34	TB_nDEVSEL : Out std_logic;\r
	35	TB_nINTA : Out std_logic );\r
62946980	36	end dhwk;\r
377c0242	37	\r
62946980	38	architecture SCHEMATIC of dhwk is\r
377c0242	39	\r
	40	SIGNAL gnd : std_logic := '0';\r
	41	SIGNAL vcc : std_logic := '1';\r
	42	\r
	43	signal READ_XX7_6 : std_logic;\r
	44	signal RESERVE : std_logic;\r
	45	signal SR_ERROR : std_logic;\r
	46	signal R_ERROR : std_logic;\r
	47	signal S_ERROR : std_logic;\r
	48	signal WRITE_XX3_2 : std_logic;\r
	49	signal WRITE_XX5_4 : std_logic;\r
	50	signal WRITE_XX7_6 : std_logic;\r
	51	signal READ_XX1_0 : std_logic;\r
	52	signal READ_XX3_2 : std_logic;\r
	53	signal INTAn : std_logic;\r
	54	signal TRDYn : std_logic;\r
	55	signal READ_XX5_4 : std_logic;\r
	56	signal DEVSELn : std_logic;\r
	57	signal FIFO_RDn : std_logic;\r
	58	signal WRITE_XX1_0 : std_logic;\r
	59	signal REG_OUT_XX6 : std_logic_vector (7 downto 0);\r
	60	signal SYNC_FLAG : std_logic_vector (7 downto 0);\r
	61	signal INT_REG : std_logic_vector (7 downto 0);\r
	62	signal REVISON_ID : std_logic_vector (7 downto 0);\r
	63	signal VENDOR_ID : std_logic_vector (15 downto 0);\r
	64	signal READ_SEL : std_logic_vector (1 downto 0);\r
	65	signal AD_REG : std_logic_vector (31 downto 0);\r
	66	signal REG_OUT_XX7 : std_logic_vector (7 downto 0);\r
2825d08e	67	signal R_EFn : std_logic;\r
	68	signal R_FFn : std_logic;\r
	69	signal R_FIFO_Q_OUT : std_logic_vector (7 downto 0);\r
	70	signal R_HFn : std_logic;\r
	71	signal S_EFn : std_logic;\r
	72	signal S_FFn : std_logic;\r
	73	signal S_FIFO_Q_OUT : std_logic_vector (7 downto 0);\r
	74	signal S_HFn : std_logic;\r
	75	signal R_FIFO_D_IN : std_logic_vector (7 downto 0);\r
	76	signal R_FIFO_READn : std_logic;\r
	77	signal R_FIFO_RESETn : std_logic;\r
	78	signal R_FIFO_RTn : std_logic;\r
	79	signal R_FIFO_WRITEn : std_logic;\r
	80	signal S_FIFO_D_IN : std_logic_vector (7 downto 0);\r
	81	signal S_FIFO_READn : std_logic;\r
	82	signal S_FIFO_RESETn : std_logic;\r
	83	signal S_FIFO_RTn : std_logic;\r
	84	signal S_FIFO_WRITEn : std_logic;\r
257c0fc1	85	signal SERIAL_IN : std_logic;\r
	86	signal SPC_RDY_IN : std_logic;\r
	87	signal SERIAL_OUT : std_logic;\r
	88	signal SPC_RDY_OUT : std_logic;\r
377c0242	89	\r
	90	component MESS_1_TB\r
	91	Port ( DEVSELn : In std_logic;\r
	92	INTAn : In std_logic;\r
	93	KONST_1 : In std_logic;\r
	94	PCI_IDSEL : In std_logic;\r
	95	REG_OUT_XX7 : In std_logic_vector (7 downto 0);\r
	96	TB_DEVSELn : Out std_logic;\r
	97	TB_INTAn : Out std_logic;\r
	98	TB_PCI_IDSEL : Out std_logic );\r
	99	end component;\r
	100	\r
	101	component VEN_REV_ID\r
	102	Port ( REV_ID : Out std_logic_vector (7 downto 0);\r
	103	VEN_ID : Out std_logic_vector (15 downto 0) );\r
	104	end component;\r
	105	\r
	106	component INTERRUPT\r
	107	Port ( INT_IN_0 : In std_logic;\r
	108	INT_IN_1 : In std_logic;\r
	109	INT_IN_2 : In std_logic;\r
	110	INT_IN_3 : In std_logic;\r
	111	INT_IN_4 : In std_logic;\r
	112	INT_IN_5 : In std_logic;\r
	113	INT_IN_6 : In std_logic;\r
	114	INT_IN_7 : In std_logic;\r
	115	INT_MASKE : In std_logic_vector (7 downto 0);\r
	116	INT_RES : In std_logic_vector (7 downto 0);\r
	117	PCI_CLOCK : In std_logic;\r
	118	PCI_RSTn : In std_logic;\r
	119	READ_XX5_4 : In std_logic;\r
	120	RESET : In std_logic;\r
	121	TAST_RESn : In std_logic;\r
	122	TAST_SETn : In std_logic;\r
	123	TRDYn : In std_logic;\r
	124	INT_REG : Out std_logic_vector (7 downto 0);\r
	125	INTAn : Out std_logic;\r
	126	PCI_INTAn : Out std_logic );\r
	127	end component;\r
	128	\r
	129	component FIFO_CONTROL\r
	130	Port ( FIFO_RDn : In std_logic;\r
	131	FLAG_IN_0 : In std_logic;\r
	132	FLAG_IN_4 : In std_logic;\r
	133	HOLD : In std_logic;\r
	134	KONST_1 : In std_logic;\r
	135	PCI_CLOCK : In std_logic;\r
	136	PSC_ENABLE : In std_logic;\r
	137	R_EFn : In std_logic;\r
	138	R_FFn : In std_logic;\r
	139	R_HFn : In std_logic;\r
	140	RESET : In std_logic;\r
	141	S_EFn : In std_logic;\r
	142	S_FFn : In std_logic;\r
	143	S_FIFO_Q_OUT : In std_logic_vector (7 downto 0);\r
	144	S_HFn : In std_logic;\r
	145	SERIAL_IN : In std_logic;\r
	146	SPC_ENABLE : In std_logic;\r
	147	SPC_RDY_IN : In std_logic;\r
	148	WRITE_XX1_0 : In std_logic;\r
	149	R_ERROR : Out std_logic;\r
	150	R_FIFO_D_IN : Out std_logic_vector (7 downto 0);\r
	151	R_FIFO_READn : Out std_logic;\r
	152	R_FIFO_RESETn : Out std_logic;\r
153	R_FIFO_RETRANSMITn : Out std_logic;\r
154	R_FIFO_WRITEn : Out std_logic;\r
155	RESERVE : Out std_logic;\r
156	S_ERROR : Out std_logic;\r
157	S_FIFO_READn : Out std_logic;\r
158	S_FIFO_RESETn : Out std_logic;\r
159	S_FIFO_RETRANSMITn : Out std_logic;\r
160	S_FIFO_WRITEn : Out std_logic;\r
161	SERIAL_OUT : Out std_logic;\r
162	SPC_RDY_OUT : Out std_logic;\r
163	SR_ERROR : Out std_logic;\r
164	SYNC_FLAG : Out std_logic_vector (7 downto 0) );\r
165	end component;\r
166	\r
167	component PCI_TOP\r
168	Port ( FLAG : In std_logic_vector (7 downto 0);\r
169	INT_REG : In std_logic_vector (7 downto 0);\r
170	PCI_CBEn : In std_logic_vector (3 downto 0);\r
171	PCI_CLOCK : In std_logic;\r
172	PCI_FRAMEn : In std_logic;\r
173	PCI_IDSEL : In std_logic;\r
174	PCI_IRDYn : In std_logic;\r
175	PCI_RSTn : In std_logic;\r
176	R_FIFO_Q : In std_logic_vector (7 downto 0);\r
177	REVISON_ID : In std_logic_vector (7 downto 0);\r
178	VENDOR_ID : In std_logic_vector (15 downto 0);\r
179	PCI_AD : InOut std_logic_vector (31 downto 0);\r
180	PCI_PAR : InOut std_logic;\r
181	AD_REG : Out std_logic_vector (31 downto 0);\r
182	DEVSELn : Out std_logic;\r
183	FIFO_RDn : Out std_logic;\r
184	PCI_DEVSELn : Out std_logic;\r
185	PCI_PERRn : Out std_logic;\r
186	PCI_SERRn : Out std_logic;\r
187	PCI_STOPn : Out std_logic;\r
188	PCI_TRDYn : Out std_logic;\r
189	READ_SEL : Out std_logic_vector (1 downto 0);\r
190	READ_XX1_0 : Out std_logic;\r
191	READ_XX3_2 : Out std_logic;\r
192	READ_XX5_4 : Out std_logic;\r
193	READ_XX7_6 : Out std_logic;\r
194	REG_OUT_XX0 : Out std_logic_vector (7 downto 0);\r
195	REG_OUT_XX6 : Out std_logic_vector (7 downto 0);\r
196	REG_OUT_XX7 : Out std_logic_vector (7 downto 0);\r
197	TRDYn : Out std_logic;\r
198	WRITE_XX1_0 : Out std_logic;\r
199	WRITE_XX3_2 : Out std_logic;\r
200	WRITE_XX5_4 : Out std_logic;\r
201	WRITE_XX7_6 : Out std_logic );\r
202	end component;\r
203	\r
2825d08e	204	component fifo_generator_v3_2\r
	205	port (\r
	206	clk: IN std_logic;\r
	207	din: IN std_logic_VECTOR(7 downto 0);\r
	208	rd_en: IN std_logic;\r
	209	rst: IN std_logic;\r
	210	wr_en: IN std_logic;\r
	211	almost_empty: OUT std_logic;\r
	212	almost_full: OUT std_logic;\r
	213	dout: OUT std_logic_VECTOR(7 downto 0);\r
	214	empty: OUT std_logic;\r
	215	full: OUT std_logic;\r
	216	prog_full: OUT std_logic);\r
	217	end component;\r
	218	\r
377c0242	219	begin\r
257c0fc1	220	SERIAL_IN <= SERIAL_OUT;\r
257c0fc1	221	SPC_RDY_IN <= SPC_RDY_OUT;\r
377c0242	222	\r
	223	I19 : MESS_1_TB\r
	224	Port Map ( DEVSELn=>DEVSELn, INTAn=>INTAn, KONST_1=>KONST_1,\r
	225	PCI_IDSEL=>PCI_IDSEL,\r
	226	REG_OUT_XX7(7 downto 0)=>REG_OUT_XX7(7 downto 0),\r
	227	TB_DEVSELn=>TB_nDEVSEL, TB_INTAn=>TB_nINTA,\r
	228	TB_PCI_IDSEL=>TB_IDSEL );\r
	229	I18 : VEN_REV_ID\r
	230	Port Map ( REV_ID(7 downto 0)=>REVISON_ID(7 downto 0),\r
	231	VEN_ID(15 downto 0)=>VENDOR_ID(15 downto 0) );\r
	232	I16 : INTERRUPT\r
	233	Port Map ( INT_IN_0=>SYNC_FLAG(1), INT_IN_1=>SYNC_FLAG(6),\r
	234	INT_IN_2=>KONST_1, INT_IN_3=>KONST_1, INT_IN_4=>KONST_1,\r
	235	INT_IN_5=>KONST_1, INT_IN_6=>KONST_1, INT_IN_7=>KONST_1,\r
	236	INT_MASKE(7 downto 0)=>REG_OUT_XX6(7 downto 0),\r
	237	INT_RES(7 downto 0)=>AD_REG(7 downto 0),\r
	238	PCI_CLOCK=>PCI_CLOCK, PCI_RSTn=>PCI_RSTn,\r
	239	READ_XX5_4=>READ_XX5_4, RESET=>REG_OUT_XX7(0),\r
	240	TAST_RESn=>TAST_RESn, TAST_SETn=>TAST_SETn,\r
	241	TRDYn=>TRDYn, INT_REG(7 downto 0)=>INT_REG(7 downto 0),\r
	242	INTAn=>INTAn, PCI_INTAn=>PCI_INTAn );\r
	243	I14 : FIFO_CONTROL\r
	244	Port Map ( FIFO_RDn=>FIFO_RDn, FLAG_IN_0=>R_ERROR,\r
	245	FLAG_IN_4=>S_ERROR, HOLD=>READ_SEL(0), KONST_1=>KONST_1,\r
	246	PCI_CLOCK=>PCI_CLOCK, PSC_ENABLE=>REG_OUT_XX7(1),\r
	247	R_EFn=>R_EFn, R_FFn=>R_FFn, R_HFn=>R_HFn,\r
	248	RESET=>REG_OUT_XX7(0), S_EFn=>S_EFn, S_FFn=>S_FFn,\r
	249	S_FIFO_Q_OUT(7 downto 0)=>S_FIFO_Q_OUT(7 downto 0),\r
	250	S_HFn=>S_HFn, SERIAL_IN=>SERIAL_IN,\r
	251	SPC_ENABLE=>REG_OUT_XX7(2), SPC_RDY_IN=>SPC_RDY_IN,\r
	252	WRITE_XX1_0=>WRITE_XX1_0, R_ERROR=>R_ERROR,\r
	253	R_FIFO_D_IN(7 downto 0)=>R_FIFO_D_IN(7 downto 0),\r
	254	R_FIFO_READn=>R_FIFO_READn,\r
	255	R_FIFO_RESETn=>R_FIFO_RESETn,\r
	256	R_FIFO_RETRANSMITn=>R_FIFO_RTn,\r
	257	R_FIFO_WRITEn=>R_FIFO_WRITEn, RESERVE=>RESERVE,\r
	258	S_ERROR=>S_ERROR, S_FIFO_READn=>S_FIFO_READn,\r
	259	S_FIFO_RESETn=>S_FIFO_RESETn,\r
	260	S_FIFO_RETRANSMITn=>S_FIFO_RTn,\r
	261	S_FIFO_WRITEn=>S_FIFO_WRITEn, SERIAL_OUT=>SERIAL_OUT,\r
	262	SPC_RDY_OUT=>SPC_RDY_OUT, SR_ERROR=>SR_ERROR,\r
	263	SYNC_FLAG(7 downto 0)=>SYNC_FLAG(7 downto 0) );\r
	264	I1 : PCI_TOP\r
	265	Port Map ( FLAG(7 downto 0)=>SYNC_FLAG(7 downto 0),\r
	266	INT_REG(7 downto 0)=>INT_REG(7 downto 0),\r
	267	PCI_CBEn(3 downto 0)=>PCI_CBEn(3 downto 0),\r
	268	PCI_CLOCK=>PCI_CLOCK, PCI_FRAMEn=>PCI_FRAMEn,\r
	269	PCI_IDSEL=>PCI_IDSEL, PCI_IRDYn=>PCI_IRDYn,\r
	270	PCI_RSTn=>PCI_RSTn,\r
	271	R_FIFO_Q(7 downto 0)=>R_FIFO_Q_OUT(7 downto 0),\r
	272	REVISON_ID(7 downto 0)=>REVISON_ID(7 downto 0),\r
	273	VENDOR_ID(15 downto 0)=>VENDOR_ID(15 downto 0),\r
	274	PCI_AD(31 downto 0)=>PCI_AD(31 downto 0),\r
	275	PCI_PAR=>PCI_PAR,\r
	276	AD_REG(31 downto 0)=>AD_REG(31 downto 0),\r
	277	DEVSELn=>DEVSELn, FIFO_RDn=>FIFO_RDn,\r
	278	PCI_DEVSELn=>PCI_DEVSELn, PCI_PERRn=>PCI_PERRn,\r
	279	PCI_SERRn=>PCI_SERRn, PCI_STOPn=>PCI_STOPn,\r
	280	PCI_TRDYn=>PCI_TRDYn,\r
	281	READ_SEL(1 downto 0)=>READ_SEL(1 downto 0),\r
	282	READ_XX1_0=>READ_XX1_0, READ_XX3_2=>READ_XX3_2,\r
	283	READ_XX5_4=>READ_XX5_4, READ_XX7_6=>READ_XX7_6,\r
	284	REG_OUT_XX0(7 downto 0)=>S_FIFO_D_IN(7 downto 0),\r
	285	REG_OUT_XX6(7 downto 0)=>REG_OUT_XX6(7 downto 0),\r
286	REG_OUT_XX7(7 downto 0)=>REG_OUT_XX7(7 downto 0),\r
287	TRDYn=>TRDYn, WRITE_XX1_0=>WRITE_XX1_0,\r
288	WRITE_XX3_2=>WRITE_XX3_2, WRITE_XX5_4=>WRITE_XX5_4,\r
289	WRITE_XX7_6=>WRITE_XX7_6 );\r
290	\r
2825d08e	291	receive_fifo : fifo_generator_v3_2\r
	292	port map (\r
	293	clk => PCI_CLOCK,\r
	294	din => R_FIFO_D_IN,\r
	295	rd_en => not R_FIFO_READn,\r
	296	rst => not R_FIFO_RESETn,\r
	297	wr_en => not R_FIFO_WRITEn,\r
	298	dout => R_FIFO_Q_OUT,\r
	299	empty => R_EFn,\r
	300	full => R_FFn,\r
	301	prog_full => R_HFn);\r
	302	\r
	303	send_fifo : fifo_generator_v3_2\r
	304	port map (\r
	305	clk => PCI_CLOCK,\r
	306	din => S_FIFO_D_IN,\r
	307	rd_en => not S_FIFO_READn,\r
	308	rst => not S_FIFO_RESETn,\r
	309	wr_en => not S_FIFO_WRITEn,\r
	310	dout => S_FIFO_Q_OUT,\r
	311	empty => S_EFn,\r
	312	full => S_FFn,\r
	313	prog_full => S_HFn);\r
377c0242	314	end SCHEMATIC;\r