[raggedstone] / dhwk / source / pci / parity_4.vhd

-- J.STELZNER
-- INFORMATIK-3 LABOR
-- 23.08.2006
-- File: PARITY_4.VHD

library ieee;
use ieee.std_logic_1164.all;

entity PARITY_4 is
        port
        (
                PAR_IN :in std_logic_vector(3 downto 0);
                PAR_OUT :out std_logic
        );
end entity PARITY_4;

architecture PARITY_4_DESIGN of PARITY_4 is

begin

        PAR_OUT <= PAR_IN(3) xor PAR_IN(2) xor PAR_IN(1) xor PAR_IN(0);

end architecture PARITY_4_DESIGN;
Commit	Line	Data
696ded12	1	-- J.STELZNER
	2	-- INFORMATIK-3 LABOR
	3	-- 23.08.2006
	4	-- File: PARITY_4.VHD
	5
	6	library ieee;
	7	use ieee.std_logic_1164.all;
	8
	9	entity PARITY_4 is
2612d712	10	port
	11	(
	12	PAR_IN :in std_logic_vector(3 downto 0);
	13	PAR_OUT :out std_logic
	14	);
	15	end entity PARITY_4;
696ded12	16
	17	architecture PARITY_4_DESIGN of PARITY_4 is
	18
	19	begin
	20
2612d712	21	PAR_OUT <= PAR_IN(3) xor PAR_IN(2) xor PAR_IN(1) xor PAR_IN(0);
696ded12	22
696ded12	23	end architecture PARITY_4_DESIGN;