[raggedstone] / dhwk_old / source / pfs.v

module pfs2 (clk, a, b);
	input clk;
	input a;
	output b;
	reg b;

	always @(posedge clk)
	begin
		b <= a;
	end
endmodule
Commit	Line	Data
ebba63a9	1	module pfs2 (clk, a, b);
	2	input clk;
	3	input a;
	4	output b;
	5	reg b;
	6
	7	always @(posedge clk)
	8	begin
	9	b <= a;
	10	end
	11	endmodule