coding style
[raggedstone] / dhwk / source / config_rd_0.vhd
CommitLineData
696ded12 1-- J.STELZNER
2-- INFORMATIK-3 LABOR
3-- 23.08.2006
4-- File: CONFIG_RD_0.VHD
5
6library IEEE;
7use IEEE.std_logic_1164.all;
8
9entity CONFIG_RD_0 is
10 port
11 (
12 ADDR_REG :in std_logic_vector (31 downto 0);
13 CF_RD_COM :in std_logic;
14 READ_SEL :out std_logic_vector ( 2 downto 0)
15 );
16end entity CONFIG_RD_0;
17
18architecture CONFIG_RD_0_DESIGN of CONFIG_RD_0 is
19
20--
21--
22--
23--
24--
25-- PCI Configuration Space Header
26--
27-- \ Bit
28-- \
29--Address |31 24|23 16|15 8|7 0|
30-----------------------------------------------------------------
31--00 |Device ID |Vendor ID |
32--04 |Status |Command |
33--08 |Class Code |Revision ID|
34--0C |BIST |Header Type|Latency T. |Cache L.S. |
35--10-24 |Base Address Register |
36--28 |Cardbus CIS Pointer |
37--2C |Subsystem ID |Subsystem Vendor ID |
38--30 |Expansion ROM Base Address |
39--34 |Reserved |
40--38 |Reserved |
41--3C |Max_Lat |Min_Gnt |Int_Pin |Int_Line |
42--40-FF | |
43-----------------------------------------------------------------
44
45
46--PCI Bus Commands
47--C/BE[3..0] Command Type
48--------------------------------------
49-- 0000 Interrupt Acknowledge
50-- 0001 Special Cycle
51-- 0010 I/O Read
52-- 0011 I/O Write
53-- 0100 Reserved
54-- 0101 Reserved
55-- 0110 Memory Read
56-- 0111 Memory Write
57--
58-- 1000 Reserved
59-- 1001 Reserved
60-- 1010 Configuration Read
61-- 1011 Configuration Write
62-- 1100 Memory Read Multiple
63-- 1101 Dual Address Cycle
64-- 1110 Memory Read Line
65-- 1111 Memory Write and Invalidate
66
67
68--PCI Byte Enable
69--C/BE[3..0] gueltige Datenbits
70-------------------------------
71-- 0000 AD 31..0
72-- 1000 AD 23..0
73-- 1100 AD 15..0
74-- 1110 AD 7..0
75
76 constant CMD_INT_ACK :std_logic_vector(3 downto 0) := "0000";
77 constant CMD_SP_CYC :std_logic_vector(3 downto 0) := "0001";
78 constant CMD_IO_READ :std_logic_vector(3 downto 0) := "0010";
79 constant CMD_IO_WRITE :std_logic_vector(3 downto 0) := "0011";
80 constant CMD_RES_4 :std_logic_vector(3 downto 0) := "0100";
81 constant CMD_RES_5 :std_logic_vector(3 downto 0) := "0101";
82 constant CMD_MEM_READ :std_logic_vector(3 downto 0) := "0110";
83 constant CMD_MEM_WRITE :std_logic_vector(3 downto 0) := "0111";
84 constant CMD_RES_8 :std_logic_vector(3 downto 0) := "1000";
85 constant CMD_RES_9 :std_logic_vector(3 downto 0) := "1001";
86 constant CMD_CONF_READ :std_logic_vector(3 downto 0) := "1010";
87 constant CMD_CONF_WRITE :std_logic_vector(3 downto 0) := "1011";
88 constant CMD_MEM_READ_M :std_logic_vector(3 downto 0) := "1100";
89 constant CMD_DU_ADR_CYC :std_logic_vector(3 downto 0) := "1101";
90 constant CMD_MEN_READ_L :std_logic_vector(3 downto 0) := "1110";
91 constant CMD_MEM_WRITE_I :std_logic_vector(3 downto 0) := "1111";
92
93 signal MUX :std_logic_vector(31 downto 0);
94 signal CONFIG_ADDR :std_logic_vector( 7 downto 0);
95
96begin
97
98 CONFIG_ADDR(7 downto 0) <= ADDR_REG(7 downto 0);
99
100--*******************************************************************
101--*********************** PCI Read Address **************************
102--*******************************************************************
103
104 process (CF_RD_COM, CONFIG_ADDR)
105 begin
106
107 if CF_RD_COM = '1' then
108
109 if CONFIG_ADDR = X"00" then READ_SEL <= "000";
110 elsif CONFIG_ADDR = X"04" then READ_SEL <= "001";
111 elsif CONFIG_ADDR = X"08" then READ_SEL <= "010";
112 elsif CONFIG_ADDR = X"10" then READ_SEL <= "011";
113 elsif CONFIG_ADDR = X"3C" then READ_SEL <= "100";
114 elsif CONFIG_ADDR = X"40" then READ_SEL <= "101";
115 else READ_SEL <= "111";
116 end if;
117 else READ_SEL <= "111";
118 end if;
119 end process;
120
121end architecture CONFIG_RD_0_DESIGN;
122
Impressum, Datenschutz