ebba63a9 |
1 | --+-------------------------------------------------------------------------------------------------+\r |
2 | --| |\r |
3 | --| File: top.vhd |\r |
4 | --| |\r |
5 | --| Components: pci32lite.vhd |\r |
6 | --| pciwbsequ.vhd |\r |
7 | --| pcidmux.vhd |\r |
8 | --| pciregs.vhd |\r |
9 | --| pcipargen.vhd |\r |
10 | --| -- Libs -- |\r |
11 | --| ona.vhd |\r |
12 | --| |\r |
13 | --| Description: RS1 PCI Demo : (TOP) Main file. |\r |
14 | --| |\r |
15 | --| |\r |
16 | --| |\r |
17 | --+-------------------------------------------------------------------------------------------------+\r |
18 | --| |\r |
19 | --| Revision history : |\r |
20 | --| Date Version Author Description |\r |
21 | --| |\r |
22 | --| |\r |
23 | --| To do: |\r |
24 | --| |\r |
25 | --+-------------------------------------------------------------------------------------------------+\r |
26 | \r |
27 | \r |
28 | --+-----------------------------------------------------------------------------+\r |
29 | --| LIBRARIES |\r |
30 | --+-----------------------------------------------------------------------------+\r |
31 | \r |
32 | library ieee;\r |
33 | use ieee.std_logic_1164.all;\r |
34 | use ieee.std_logic_arith.all;\r |
35 | use ieee.std_logic_unsigned.all;\r |
36 | \r |
37 | --+-----------------------------------------------------------------------------+\r |
38 | --| ENTITY |\r |
39 | --+-----------------------------------------------------------------------------+\r |
40 | \r |
41 | entity dhwk is\r |
42 | port (\r |
43 | \r |
44 | -- General \r |
45 | PCI_CLK : in std_logic;\r |
46 | PCI_nRES : in std_logic;\r |
47 | \r |
48 | -- PCI target 32bits\r |
49 | PCI_AD : inout std_logic_vector(31 downto 0);\r |
50 | PCI_CBE : in std_logic_vector(3 downto 0);\r |
51 | PCI_PAR : out std_logic; \r |
52 | PCI_nFRAME : in std_logic;\r |
53 | PCI_nIRDY : in std_logic;\r |
54 | PCI_nTRDY : out std_logic;\r |
55 | PCI_nDEVSEL : out std_logic;\r |
56 | PCI_nSTOP : out std_logic;\r |
57 | PCI_IDSEL : in std_logic;\r |
58 | PCI_nPERR : out std_logic;\r |
59 | PCI_nSERR : out std_logic;\r |
60 | PCI_nINT : out std_logic;\r |
61 | \r |
62 | -- debug signals\r |
63 | LED3 : out std_logic;\r |
64 | LED2 : out std_logic;\r |
65 | LED4 : out std_logic;\r |
66 | LED5 : out std_logic\r |
67 | \r |
68 | );\r |
69 | end dhwk;\r |
70 | \r |
71 | \r |
72 | --+-----------------------------------------------------------------------------+\r |
73 | --| ARCHITECTURE |\r |
74 | --+-----------------------------------------------------------------------------+\r |
75 | \r |
76 | architecture dhwk_arch of dhwk is\r |
77 | \r |
78 | \r |
79 | --+-----------------------------------------------------------------------------+\r |
80 | --| COMPONENTS |\r |
81 | --+-----------------------------------------------------------------------------+\r |
82 | \r |
83 | component pci32tlite\r |
84 | port (\r |
85 | \r |
86 | -- General \r |
87 | clk33 : in std_logic;\r |
88 | nrst : in std_logic;\r |
89 | \r |
90 | -- PCI target 32bits\r |
91 | ad : inout std_logic_vector(31 downto 0);\r |
92 | cbe : in std_logic_vector(3 downto 0);\r |
93 | par : out std_logic; \r |
94 | frame : in std_logic;\r |
95 | irdy : in std_logic;\r |
96 | trdy : out std_logic;\r |
97 | devsel : out std_logic;\r |
98 | stop : out std_logic;\r |
99 | idsel : in std_logic;\r |
100 | perr : out std_logic;\r |
101 | serr : out std_logic;\r |
102 | intb : out std_logic;\r |
103 | \r |
104 | -- Master whisbone\r |
105 | wb_adr_o : out std_logic_vector(24 downto 1); \r |
106 | wb_dat_i : in std_logic_vector(15 downto 0);\r |
107 | wb_dat_o : out std_logic_vector(15 downto 0);\r |
108 | wb_sel_o : out std_logic_vector(1 downto 0);\r |
109 | wb_we_o : out std_logic;\r |
110 | wb_stb_o : out std_logic;\r |
111 | wb_cyc_o : out std_logic;\r |
112 | wb_ack_i : in std_logic;\r |
113 | wb_err_i : in std_logic;\r |
114 | wb_int_i : in std_logic;\r |
115 | \r |
116 | -- debug signals\r |
117 | debug_init : out std_logic;\r |
118 | debug_access : out std_logic \r |
119 | \r |
120 | );\r |
121 | end component;\r |
122 | \r |
123 | component heartbeat\r |
124 | port (\r |
125 | clk_i : in std_logic;\r |
126 | nrst_i : in std_logic;\r |
127 | led2_o : out std_logic;\r |
128 | led3_o : out std_logic;\r |
129 | led4_o : out std_logic;\r |
130 | led5_o : out std_logic\r |
131 | );\r |
132 | end component;\r |
133 | \r |
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134 | component generic_fifo_sc_a\r |
135 | port (\r |
136 | clk : in std_logic;\r |
137 | rst : in std_logic;\r |
138 | clr : in std_logic;\r |
139 | din : in std_logic_vector(7 downto 0);\r |
140 | we : in std_logic;\r |
141 | dout : out std_logic_vector(7 downto 0);\r |
142 | re : in std_logic;\r |
143 | full : out std_logic;\r |
144 | full_r : out std_logic;\r |
145 | empty : out std_logic;\r |
146 | empty_r : out std_logic;\r |
147 | full_n : out std_logic;\r |
148 | full_n_r : out std_logic;\r |
149 | empty_n : out std_logic;\r |
150 | empty_n_r : out std_logic;\r |
151 | level : out std_logic_vector(1 downto 0)\r |
152 | );\r |
153 | end component;\r |
154 | \r |
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155 | \r |
156 | --+-----------------------------------------------------------------------------+\r |
157 | --| CONSTANTS |\r |
158 | --+-----------------------------------------------------------------------------+\r |
159 | --+-----------------------------------------------------------------------------+\r |
160 | --| SIGNALS |\r |
161 | --+-----------------------------------------------------------------------------+\r |
162 | \r |
163 | signal wb_adr : std_logic_vector(24 downto 1); \r |
164 | signal wb_dat_out : std_logic_vector(15 downto 0);\r |
165 | signal wb_dat_in : std_logic_vector(15 downto 0);\r |
166 | signal wb_sel : std_logic_vector(1 downto 0);\r |
167 | signal wb_we : std_logic;\r |
168 | signal wb_stb : std_logic;\r |
169 | signal wb_cyc : std_logic;\r |
170 | signal wb_ack : std_logic;\r |
171 | signal wb_err : std_logic;\r |
172 | signal wb_int : std_logic;\r |
173 | \r |
174 | \r |
175 | begin\r |
176 | \r |
177 | --+-----------------------------------------+\r |
178 | --| PCI Target |\r |
179 | --+-----------------------------------------+\r |
180 | \r |
181 | u_pci: component pci32tlite\r |
182 | port map(\r |
183 | clk33 => PCI_CLK,\r |
184 | nrst => PCI_nRES,\r |
185 | ad => PCI_AD,\r |
186 | cbe => PCI_CBE,\r |
187 | par => PCI_PAR,\r |
188 | frame => PCI_nFRAME,\r |
189 | irdy => PCI_nIRDY,\r |
190 | trdy => PCI_nTRDY,\r |
191 | devsel => PCI_nDEVSEL,\r |
192 | stop => PCI_nSTOP,\r |
193 | idsel => PCI_IDSEL,\r |
194 | perr => PCI_nPERR,\r |
195 | serr => PCI_nSERR,\r |
196 | intb => PCI_nINT,\r |
197 | wb_adr_o => wb_adr, \r |
198 | wb_dat_i => wb_dat_out,\r |
199 | wb_dat_o => wb_dat_in,\r |
200 | wb_sel_o => wb_sel, \r |
201 | wb_we_o => wb_we,\r |
202 | wb_stb_o => wb_stb, \r |
203 | wb_cyc_o => wb_cyc,\r |
204 | wb_ack_i => wb_ack,\r |
205 | wb_err_i => wb_err,\r |
206 | wb_int_i => wb_int\r |
207 | -- debug_init => LED3,\r |
208 | -- debug_access => LED2\r |
209 | );\r |
210 | \r |
211 | --+-----------------------------------------+\r |
212 | --| WB-7seg |\r |
213 | --+-----------------------------------------+\r |
214 | \r |
215 | my_heartbeat: component heartbeat\r |
216 | port map( \r |
217 | clk_i => PCI_CLK,\r |
218 | nrst_i => PCI_nRES,\r |
219 | led2_o => LED2,\r |
220 | led3_o => LED3,\r |
221 | led4_o => LED4,\r |
222 | led5_o => LED5\r |
223 | );\r |
224 | \r |
225 | end dhwk_arch;\r |