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1 | library ieee;\r |
2 | use ieee.std_logic_1164.all;\r |
3 | use ieee.std_logic_arith.all;\r |
4 | use ieee.std_logic_unsigned.all;\r |
5 | \r |
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6 | entity dhwk is\r |
7 | port (\r |
8 | \r |
9 | -- General \r |
10 | PCI_CLK : in std_logic;\r |
11 | PCI_nRES : in std_logic;\r |
12 | \r |
13 | -- PCI target 32bits\r |
14 | PCI_AD : inout std_logic_vector(31 downto 0);\r |
15 | PCI_CBE : in std_logic_vector(3 downto 0);\r |
16 | PCI_PAR : out std_logic; \r |
17 | PCI_nFRAME : in std_logic;\r |
18 | PCI_nIRDY : in std_logic;\r |
19 | PCI_nTRDY : out std_logic;\r |
20 | PCI_nDEVSEL : out std_logic;\r |
21 | PCI_nSTOP : out std_logic;\r |
22 | PCI_IDSEL : in std_logic;\r |
23 | PCI_nPERR : out std_logic;\r |
24 | PCI_nSERR : out std_logic;\r |
25 | PCI_nINT : out std_logic;\r |
26 | \r |
27 | -- debug signals\r |
28 | LED3 : out std_logic;\r |
29 | LED2 : out std_logic;\r |
30 | LED4 : out std_logic;\r |
31 | LED5 : out std_logic\r |
32 | \r |
33 | );\r |
34 | end dhwk;\r |
35 | \r |
36 | \r |
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37 | architecture dhwk_arch of dhwk is\r |
38 | \r |
39 | \r |
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40 | component pci32tlite\r |
41 | port (\r |
42 | \r |
43 | -- General \r |
44 | clk33 : in std_logic;\r |
45 | nrst : in std_logic;\r |
46 | \r |
47 | -- PCI target 32bits\r |
48 | ad : inout std_logic_vector(31 downto 0);\r |
49 | cbe : in std_logic_vector(3 downto 0);\r |
50 | par : out std_logic; \r |
51 | frame : in std_logic;\r |
52 | irdy : in std_logic;\r |
53 | trdy : out std_logic;\r |
54 | devsel : out std_logic;\r |
55 | stop : out std_logic;\r |
56 | idsel : in std_logic;\r |
57 | perr : out std_logic;\r |
58 | serr : out std_logic;\r |
59 | intb : out std_logic;\r |
60 | \r |
61 | -- Master whisbone\r |
62 | wb_adr_o : out std_logic_vector(24 downto 1); \r |
63 | wb_dat_i : in std_logic_vector(15 downto 0);\r |
64 | wb_dat_o : out std_logic_vector(15 downto 0);\r |
65 | wb_sel_o : out std_logic_vector(1 downto 0);\r |
66 | wb_we_o : out std_logic;\r |
67 | wb_stb_o : out std_logic;\r |
68 | wb_cyc_o : out std_logic;\r |
69 | wb_ack_i : in std_logic;\r |
70 | wb_err_i : in std_logic;\r |
71 | wb_int_i : in std_logic;\r |
72 | \r |
73 | -- debug signals\r |
74 | debug_init : out std_logic;\r |
75 | debug_access : out std_logic \r |
76 | \r |
77 | );\r |
78 | end component;\r |
79 | \r |
80 | component heartbeat\r |
81 | port (\r |
82 | clk_i : in std_logic;\r |
83 | nrst_i : in std_logic;\r |
84 | led2_o : out std_logic;\r |
85 | led3_o : out std_logic;\r |
86 | led4_o : out std_logic;\r |
87 | led5_o : out std_logic\r |
88 | );\r |
89 | end component;\r |
90 | \r |
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91 | component generic_fifo_sc_a\r |
92 | port (\r |
93 | clk : in std_logic;\r |
94 | rst : in std_logic;\r |
95 | clr : in std_logic;\r |
96 | din : in std_logic_vector(7 downto 0);\r |
97 | we : in std_logic;\r |
98 | dout : out std_logic_vector(7 downto 0);\r |
99 | re : in std_logic;\r |
100 | full : out std_logic;\r |
101 | full_r : out std_logic;\r |
102 | empty : out std_logic;\r |
103 | empty_r : out std_logic;\r |
104 | full_n : out std_logic;\r |
105 | full_n_r : out std_logic;\r |
106 | empty_n : out std_logic;\r |
107 | empty_n_r : out std_logic;\r |
108 | level : out std_logic_vector(1 downto 0)\r |
109 | );\r |
110 | end component;\r |
111 | \r |
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112 | component wb_fifo\r |
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113 | port (\r |
114 | clk_i : in std_logic;\r |
115 | nrst_i : in std_logic;\r |
116 | \r |
117 | wb_adr_i : in std_logic_vector(24 downto 1);\r |
118 | wb_dat_o : out std_logic_vector(15 downto 0);\r |
119 | wb_dat_i : in std_logic_vector(15 downto 0);\r |
120 | wb_sel_i : in std_logic_vector(1 downto 0);\r |
121 | wb_we_i : in std_logic;\r |
122 | wb_stb_i : in std_logic;\r |
123 | wb_cyc_i : in std_logic;\r |
124 | wb_ack_o : out std_logic;\r |
125 | wb_err_o : out std_logic;\r |
126 | wb_int_o : out std_logic;\r |
127 | \r |
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128 | fifo_data_i : in std_logic_vector(7 downto 0);\r |
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129 | fifo_data_o : out std_logic_vector(7 downto 0);\r |
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130 | \r |
131 | fifo_we_out : out std_logic;\r |
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132 | fifo_re_out : out std_logic\r |
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133 | );\r |
134 | end component;\r |
135 | \r |
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136 | signal wb_adr : std_logic_vector(24 downto 1); \r |
137 | signal wb_dat_out : std_logic_vector(15 downto 0);\r |
138 | signal wb_dat_in : std_logic_vector(15 downto 0);\r |
139 | signal wb_sel : std_logic_vector(1 downto 0);\r |
140 | signal wb_we : std_logic;\r |
141 | signal wb_stb : std_logic;\r |
142 | signal wb_cyc : std_logic;\r |
143 | signal wb_ack : std_logic;\r |
144 | signal wb_err : std_logic;\r |
145 | signal wb_int : std_logic;\r |
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146 | \r |
147 | \r |
148 | begin\r |
149 | \r |
ebba63a9 |
150 | u_pci: component pci32tlite\r |
151 | port map(\r |
152 | clk33 => PCI_CLK,\r |
153 | nrst => PCI_nRES,\r |
154 | ad => PCI_AD,\r |
155 | cbe => PCI_CBE,\r |
156 | par => PCI_PAR,\r |
157 | frame => PCI_nFRAME,\r |
158 | irdy => PCI_nIRDY,\r |
159 | trdy => PCI_nTRDY,\r |
160 | devsel => PCI_nDEVSEL,\r |
161 | stop => PCI_nSTOP,\r |
162 | idsel => PCI_IDSEL,\r |
163 | perr => PCI_nPERR,\r |
164 | serr => PCI_nSERR,\r |
165 | intb => PCI_nINT,\r |
166 | wb_adr_o => wb_adr, \r |
167 | wb_dat_i => wb_dat_out,\r |
168 | wb_dat_o => wb_dat_in,\r |
169 | wb_sel_o => wb_sel, \r |
170 | wb_we_o => wb_we,\r |
171 | wb_stb_o => wb_stb, \r |
172 | wb_cyc_o => wb_cyc,\r |
173 | wb_ack_i => wb_ack,\r |
174 | wb_err_i => wb_err,\r |
175 | wb_int_i => wb_int\r |
176 | -- debug_init => LED3,\r |
177 | -- debug_access => LED2\r |
178 | );\r |
179 | \r |
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180 | my_heartbeat: component heartbeat\r |
181 | port map( \r |
182 | clk_i => PCI_CLK,\r |
183 | nrst_i => PCI_nRES,\r |
184 | led2_o => LED2,\r |
185 | led3_o => LED3,\r |
186 | led4_o => LED4,\r |
187 | led5_o => LED5\r |
188 | );\r |
189 | \r |
190 | end dhwk_arch;\r |