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[raggedstone] / dhwk / source / pci / config_space_header.vhd
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696ded12 1-- VHDL model created from schematic config_space_header.sch -- Jan 09 09:34:16 2007
2
696ded12 3LIBRARY ieee;
4
5USE ieee.std_logic_1164.ALL;
6USE ieee.numeric_std.ALL;
7
8
9entity CONFIG_SPACE_HEADER is
2612d712 10 Port ( AD_REG : In std_logic_vector (31 downto 0);
11 ADDR_REG : In std_logic_vector (31 downto 0);
12 CBE_REGn : In std_logic_vector (3 downto 0);
13 CF_RD_COM : In std_logic;
14 CF_WR_COM : In std_logic;
15 IRDY_REGn : In std_logic;
16 PCI_CLOCK : In std_logic;
17 PCI_RSTn : In std_logic;
18 PERR : In std_logic;
19 REVISION_ID : In std_logic_vector (7 downto 0);
20 SERR : In std_logic;
21 TRDYn : In std_logic;
22 VENDOR_ID : In std_logic_vector (15 downto 0);
23 CONF_DATA : Out std_logic_vector (31 downto 0);
24 CONF_DATA_04H : Out std_logic_vector (31 downto 0);
25 CONF_DATA_10H : Out std_logic_vector (31 downto 0) );
696ded12 26end CONFIG_SPACE_HEADER;
27
28architecture SCHEMATIC of CONFIG_SPACE_HEADER is
29
ffdaba18 30 constant CONF_DEVICE_ID :std_logic_vector(31 downto 16) := X"AFFE";
e90b12fe 31 --other comm. device
32 constant CONF_CLASS_CODE :std_logic_vector (31 downto 8) := X"078000";
ffdaba18 33
6d5ab91b 34 signal CONF_MAX_LAT :std_logic_vector (31 downto 24);
35 signal CONF_MIN_GNT :std_logic_vector (23 downto 16);
36 signal CONF_INT_PIN :std_logic_vector (15 downto 8);
37 signal CONF_INT_LINE :std_logic_vector ( 7 downto 0);
38
2a7d0ce6 39 signal CONF_BAS_ADDR_REG :std_logic_vector(31 downto 0);
40
816293e0 41 signal CONF_STATUS :std_logic_vector(31 downto 16);
42 signal CONF_COMMAND :std_logic_vector(15 downto 0);
43
7f64ffff 44 -- PCI Configuration Space Header
45 --
46 -- \ Bit
47 -- \
48 --Address |31 24|23 16|15 8|7 0|
49 -----------------------------------------------------------------
50 --00 |Device ID |Vendor ID |
51 --04 |Status |Command |
52 --08 |Class Code |Revision ID |
53 --0C |BIST |Header Type |Latency T. |Cache L.S. |
54 --10-24 |Base Address Register |
55 --28 |Cardbus CIS Pointer |
56 --2C |Subsystem ID |Subsystem Vendor ID |
57 --30 |Expansion ROM Base Address |
58 --34 |Reserved |
59 --38 |Reserved |
60 --3C |Max_Lat |Min_Gnt |Int_Pin |Int_Line |
61 --40-FF | |
62 -----------------------------------------------------------------
63
64
65 --PCI Bus Commands
66 --C/BE[3..0] Command Type
67 --------------------------------------
68 -- 0000 Interrupt Acknowledge
69 -- 0001 Special Cycle
70 -- 0010 I/O Read
71 -- 0011 I/O Write
72 -- 0100 Reserved
73 -- 0101 Reserved
74 -- 0110 Memory Read
75 -- 0111 Memory Write
76 --
77 -- 1000 Reserved
78 -- 1001 Reserved
79 -- 1010 Configuration Read
80 -- 1011 Configuration Write
81 -- 1100 Memory Read Multiple
82 -- 1101 Dual Address Cycle
83 -- 1110 Memory Read Line
84 -- 1111 Memory Write and Invalidate
85
86
87 --PCI Byte Enable
88 --C/BE[3..0] gueltige Datenbits
89 -------------------------------
90 -- 0000 AD 31..0
91 -- 1000 AD 23..0
92 -- 1100 AD 15..0
93 -- 1110 AD 7..0
94
95 constant CMD_INT_ACK :std_logic_vector(3 downto 0) := "0000";
96 constant CMD_SP_CYC :std_logic_vector(3 downto 0) := "0001";
97 constant CMD_IO_READ :std_logic_vector(3 downto 0) := "0010";
98 constant CMD_IO_WRITE :std_logic_vector(3 downto 0) := "0011";
99 constant CMD_RES_4 :std_logic_vector(3 downto 0) := "0100";
100 constant CMD_RES_5 :std_logic_vector(3 downto 0) := "0101";
101 constant CMD_MEM_READ :std_logic_vector(3 downto 0) := "0110";
102 constant CMD_MEM_WRITE :std_logic_vector(3 downto 0) := "0111";
103 constant CMD_RES_8 :std_logic_vector(3 downto 0) := "1000";
104 constant CMD_RES_9 :std_logic_vector(3 downto 0) := "1001";
105 constant CMD_CONF_READ :std_logic_vector(3 downto 0) := "1010";
106 constant CMD_CONF_WRITE :std_logic_vector(3 downto 0) := "1011";
107 constant CMD_MEM_READ_M :std_logic_vector(3 downto 0) := "1100";
108 constant CMD_DU_ADR_CYC :std_logic_vector(3 downto 0) := "1101";
109 constant CMD_MEN_READ_L :std_logic_vector(3 downto 0) := "1110";
110 constant CMD_MEM_WRITE_I :std_logic_vector(3 downto 0) := "1111";
111
112 signal CONFIG_ADDR :std_logic_vector(7 downto 0);
113 signal CONFIG_WRITE :std_logic_vector(3 downto 0);
114
115 ----
116 ----
117
2612d712 118 SIGNAL gnd : std_logic := '0';
119 SIGNAL vcc : std_logic := '1';
120
121 signal CONF_WR_04H : std_logic;
122 signal CONF_WR_10H : std_logic;
123 signal CONF_WR_3CH : std_logic;
124 signal CONF_READ_SEL : std_logic_vector (2 downto 0);
2612d712 125 signal CONF_DATA_04H_DUMMY : std_logic_vector (31 downto 0);
126 signal CONF_DATA_3CH : std_logic_vector (31 downto 0);
127 signal CONF_DATA_08H : std_logic_vector (31 downto 0);
128 signal CONF_DATA_00H : std_logic_vector (31 downto 0);
129
2612d712 130 component CONFIG_RD_0
131 Port ( ADDR_REG : In std_logic_vector (31 downto 0);
132 CF_RD_COM : In std_logic;
133 READ_SEL : Out std_logic_vector (2 downto 0) );
134 end component;
135
696ded12 136begin
ffdaba18 137 CONF_DATA_00H <= CONF_DEVICE_ID & VENDOR_ID;
e90b12fe 138 CONF_DATA_08H <= CONF_CLASS_CODE & REVISION_ID;
816293e0 139 CONF_DATA_04H <= CONF_STATUS & CONF_COMMAND;
2612d712 140
6d5ab91b 141 CONF_MAX_LAT <= X"00";
142 CONF_MIN_GNT <= X"00";
143 -- CONF_INT_PIN <= X"00"; -- Interrupt -
144 CONF_INT_PIN <= X"01"; -- Interrupt A
145 -- CONF_INT_PIN <= X"02"; -- Interrupt B
146 -- CONF_INT_PIN <= X"03"; -- Interrupt C
147 -- CONF_INT_PIN <= X"04"; -- Interrupt D
148 -- CONF_INT_PIN <= X"05 - FF0"; -- Reserviert
149 CONF_DATA_3CH <= CONF_MAX_LAT & CONF_MIN_GNT & CONF_INT_PIN & CONF_INT_LINE;
150
2a7d0ce6 151 CONF_BAS_ADDR_REG(1 downto 0) <= "01";-- Base Address Register for "I/O"
152 CONF_BAS_ADDR_REG(3 downto 2) <= "00";-- IO Bereich = 16 BYTE
153 CONF_DATA_10H <= CONF_BAS_ADDR_REG;
154
2612d712 155 I9 : CONFIG_RD_0
156 Port Map ( ADDR_REG(31 downto 0)=>ADDR_REG(31 downto 0),
157 CF_RD_COM=>CF_RD_COM,
158 READ_SEL(2 downto 0)=>CONF_READ_SEL(2 downto 0) );
696ded12 159
6d5ab91b 160 process (PCI_CLOCK,PCI_RSTn)
161 begin
2a7d0ce6 162 if PCI_RSTn = '0' then
163 CONF_INT_LINE <= (others => '0');
164
165 elsif (rising_edge(PCI_CLOCK)) then
166 if CONF_WR_3CH = '1'and CBE_REGn(0) = '0' then
167 CONF_INT_LINE(7 downto 0) <= AD_REG(7 downto 0);
168 end if;
169 end if;
170 end process;
171
172 process (PCI_CLOCK,PCI_RSTn)
173 begin
174
175 -- if PCI_RSTn = '0' then CONF_BAS_ADDR_REG(31 downto 2) <= (others =>'0');
176 if PCI_RSTn = '0' then
177 CONF_BAS_ADDR_REG(31 downto 4) <= (others =>'0');
178
179 elsif (rising_edge(PCI_CLOCK)) then
180
181 if CONF_WR_10H = '1'and CBE_REGn(3) = '0' then
182 CONF_BAS_ADDR_REG(31 downto 24) <= AD_REG(31 downto 24);
183 else
184 CONF_BAS_ADDR_REG(31 downto 24) <= CONF_BAS_ADDR_REG(31 downto 24);
185 end if;
186
187 if CONF_WR_10H = '1'and CBE_REGn(2) = '0' then
188 CONF_BAS_ADDR_REG(23 downto 16) <= AD_REG(23 downto 16);
189 else
190 CONF_BAS_ADDR_REG(23 downto 16) <= CONF_BAS_ADDR_REG(23 downto 16);
191 end if;
192
193 if CONF_WR_10H = '1'and CBE_REGn(1) = '0' then
194 CONF_BAS_ADDR_REG(15 downto 8) <= AD_REG(15 downto 8);
195 else
196 CONF_BAS_ADDR_REG(15 downto 8) <= CONF_BAS_ADDR_REG(15 downto 8);
197 end if;
198
199 -- if CONF_WR_10H = '1'and CBE_REGn(0) = '0' then
200 -- CONF_BAS_ADDR_REG( 7 downto 2) <= AD_REG( 7 downto 2);
201 -- else
202 -- CONF_BAS_ADDR_REG( 7 downto 2) <= CONF_BAS_ADDR_REG( 7 downto 2);
203 -- end if;
6d5ab91b 204
2a7d0ce6 205 if CONF_WR_10H = '1'and CBE_REGn(0) = '0' then
206 CONF_BAS_ADDR_REG( 7 downto 4) <= AD_REG( 7 downto 4);
207 else
208 CONF_BAS_ADDR_REG( 7 downto 4) <= CONF_BAS_ADDR_REG( 7 downto 4);
6d5ab91b 209 end if;
2a7d0ce6 210 end if;
6d5ab91b 211 end process;
816293e0 212
213 --*******************************************************************
214 --************* PCI Configuration Space Header "STATUS" *************
215 --*******************************************************************
216
217 CONF_STATUS(20 downto 16) <= "00000";-- Reserved
218 CONF_STATUS(21 ) <= '0';-- MAS/TAR: "R_O" :'0'= 33MHz / '1'= 66MHz
219 CONF_STATUS(22 ) <= '0';-- MAS/TAR: "R_O"
220 CONF_STATUS(23 ) <= '0';-- ???/???: "R_O" : fast back-to-back
221 CONF_STATUS(24 ) <= '0';-- Master :
222 --CONF_STATUS(26 downto 25) <= "00";-- Mas/Tar: "R_O" : timing fast for "DEVSEL"
223 CONF_STATUS(26 downto 25) <= "01";-- Mas/Tar: "R_O" : timing medium for "DEVSEL"
224 --CONF_STATUS(26 downto 25) <= "10";-- Mas/Tar: "R_O" : timing slow for "DEVSEL"
225 --CONF_STATUS(26 downto 25) <= "11";-- Mas/Tar: "R_O" : reserved
226 CONF_STATUS(27 ) <= '0';-- Target : "R_W" : Taget-Abort
227 CONF_STATUS(28 ) <= '0';-- Master : "R_W" : Taget-Abort
228 CONF_STATUS(29 ) <= '0';-- Master : "R_W" : Master-Abort
229 --CONF_STATUS(30 ) <= SERR;-- Mas/Tar: "R_W" : SERR
230 --CONF_STATUS(31 ) <= PERR;-- Mas/Tar: "R_W" : PERR
231
232 process (PCI_CLOCK,PCI_RSTn)
233 begin
234 if PCI_RSTn = '0' then
235 CONF_STATUS(30) <= '0';
236 CONF_STATUS(31) <= '0';
237
238 elsif (rising_edge(PCI_CLOCK)) then
239 if CONF_WR_04H = '1' and CBE_REGn(3) = '0' then
240 CONF_STATUS(30) <= not (AD_REG(30) and CONF_STATUS(30));
241 CONF_STATUS(31) <= not (AD_REG(31) and CONF_STATUS(31));
242
243 else
244 CONF_STATUS(30) <= SERR or CONF_STATUS(30);
245 CONF_STATUS(31) <= PERR or CONF_STATUS(31);
246
247 end if;
248 end if;
249 end process;
250
251 --*******************************************************************
252 --*********** PCI Configuration Space Header "COMMAND" **************
253 --*******************************************************************
254
255 -- CONF_COMMAND( 0) <= '0';-- I/O Space accesses ???
256 -- CONF_COMMAND( 1) <= '0';-- Mem Space accesses ???
257 -- CONF_COMMAND( 2) <= '0';-- abillity to act as a master on the PCI bus
258 -- CONF_COMMAND( 3) <= '0';-- Special Cycle ???
259 -- CONF_COMMAND( 4) <= '0';-- Master ???
260 -- CONF_COMMAND( 5) <= '0';-- VGA ???
261 -- CONF_COMMAND( 6) <= '0';-- Party checking enable/disable
262 CONF_COMMAND( 7) <= '0';-- address/data stepping ???
263 -- CONF_COMMAND( 8) <= '0';-- enable/disable "PCI_SERRn"
264 -- CONF_COMMAND( 9) <= '0';-- fast back-to-back
265 -- CONF_COMMAND(10) <= '0';-- Reserved
266 -- CONF_COMMAND(11) <= '0';-- Reserved
267 -- CONF_COMMAND(12) <= '0';-- Reserved
268 -- CONF_COMMAND(13) <= '0';-- Reserved
269 -- CONF_COMMAND(14) <= '0';-- Reserved
270 -- CONF_COMMAND(15) <= '0';-- Reserved
271
272 process (PCI_CLOCK,PCI_RSTn)
273 begin
274 if PCI_RSTn = '0' then
275 CONF_COMMAND(15 downto 8) <= (others =>'0');
276 CONF_COMMAND( 6 downto 0) <= (others =>'0');
277
278 elsif (rising_edge(PCI_CLOCK)) then
279
280 if CONF_WR_04H = '1'and CBE_REGn(1) = '0' then
281 CONF_COMMAND(15 downto 8) <= AD_REG(15 downto 8);
282 else
283 CONF_COMMAND(15 downto 8) <= CONF_COMMAND(15 downto 8);
284 end if;
285
286 if CONF_WR_04H = '1'and CBE_REGn(0) = '0' then
287 CONF_COMMAND( 6 downto 0) <= AD_REG( 6 downto 0);
288 else
289 CONF_COMMAND( 6 downto 0) <= CONF_COMMAND( 6 downto 0);
290 end if;
291 end if;
292 end process;
7f64ffff 293
294
295 --*******************************************************************
296 --******************* PCI Write Configuration Address ***************
297 --*******************************************************************
298
299 CONFIG_ADDR(7 downto 0) <= ADDR_REG(7 downto 0);
300
301
302 process (CF_WR_COM,IRDY_REGn,TRDYn,CONFIG_ADDR)
303 begin
304
305 if CF_WR_COM = '1' and IRDY_REGn = '0' and TRDYn = '0' then
306
307 if CONFIG_ADDR = X"04" then
308 CONFIG_WRITE <= "0001";
309
310 elsif CONFIG_ADDR = X"10" then
311 CONFIG_WRITE <= "0010";
312
313 elsif CONFIG_ADDR = X"3C" then
314 CONFIG_WRITE <= "0100";
315
316 -- elsif CONFIG_ADDR = X"40" then
317 -- CONFIG_WRITE <= "1000";
318 else
319 CONFIG_WRITE <= "0000";
320 end if;
321 else
322 CONFIG_WRITE <= "0000";
323 end if;
324 end process;
325
326 CONF_WR_04H <= CONFIG_WRITE(0);
327 CONF_WR_10H <= CONFIG_WRITE(1);
328 CONF_WR_3CH <= CONFIG_WRITE(2);
329 --CONF_WR_40H <= CONFIG_WRITE(3);
330
696ded12 331end SCHEMATIC;
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