[raggedstone] / dhwk / source / ven_rev_id.vhd

-- J.STELZNER\r
-- INFORMATIK-3 LABOR\r
-- 23.08.2006\r
-- File: VEN_REV_ID.VHD\r
\r
library IEEE;\r
use IEEE.std_logic_1164.all;\r
\r
entity VEN_REV_ID is\r
	port\r
	(\r
	VEN_ID	:out	std_logic_vector(15 downto 0);\r
	REV_ID	:out	std_logic_vector( 7 downto 0)\r
	);\r
end entity VEN_REV_ID;\r
\r
architecture VEN_REV_ID_DESIGN of VEN_REV_ID is\r
\r
begin\r
\r
	VEN_ID	<= X"2222";\r
	REV_ID	<= X"01";\r
\r
end architecture VEN_REV_ID_DESIGN;\r
Commit	Line	Data
fdb87310	1	-- J.STELZNER\r
	2	-- INFORMATIK-3 LABOR\r
	3	-- 23.08.2006\r
	4	-- File: VEN_REV_ID.VHD\r
	5	\r
	6	library IEEE;\r
	7	use IEEE.std_logic_1164.all;\r
	8	\r
	9	entity VEN_REV_ID is\r
	10	port\r
	11	(\r
	12	VEN_ID :out std_logic_vector(15 downto 0);\r
	13	REV_ID :out std_logic_vector( 7 downto 0)\r
	14	);\r
	15	end entity VEN_REV_ID;\r
	16	\r
	17	architecture VEN_REV_ID_DESIGN of VEN_REV_ID is\r
	18	\r
	19	begin\r
	20	\r
	21	VEN_ID <= X"2222";\r
	22	REV_ID <= X"01";\r
	23	\r
	24	end architecture VEN_REV_ID_DESIGN;\r