do something with the fifo stuff
[raggedstone] / dhwk_old / source / wb_fifo.v
CommitLineData
b125f15f 1module wb_fifo (clk_i, nrst_i, wb_adr_i, wb_dat_o, wb_dat_i, wb_sel_i, wb_we_i, \r
c53499b1 2 wb_stb_i, wb_cyc_i, wb_ack_o, wb_err_o, wb_int_o, fifo_data_i, fifo_data_o, fifo_we_o, fifo_re_o);\r
3\r
4 input clk_i;\r
5 input nrst_i;\r
6 input [24:1] wb_adr_i;\r
7 output [15:0] wb_dat_o;\r
8 input [15:0] wb_dat_i;\r
9 input [1:0] wb_sel_i;\r
10 input wb_we_i;\r
11 input wb_stb_i;\r
12 input wb_cyc_i;\r
13 output wb_ack_o;\r
14 output wb_err_o;\r
15 output wb_int_o;\r
71dc61b4 16 input [7:0] fifo_data_i;\r
17 output [7:0] fifo_data_o;\r
c53499b1 18 output fifo_we_o;\r
71dc61b4 19 output fifo_re_o;\r
c53499b1 20\r
43785e2b 21 reg [15:0] data_reg;\r
c53499b1 22\r
23 always @(posedge clk_i or negedge nrst_i)\r
24 begin\r
25 if (nrst_i == 0)\r
43785e2b 26 data_reg <= 16'h0000;\r
c53499b1 27 else \r
43785e2b 28 if (wb_stb_i && wb_we_i)\r
29 data_reg <= wb_dat_i;\r
c53499b1 30 end\r
31\r
8e9deeba 32 assign fifo_we_o = 1'b1;\r
33 assign fifo_data_o = data_reg;\r
fbd7beb9 34\r
c53499b1 35 assign wb_ack_o = wb_stb_i;\r
36 assign wb_err_o = 1'b0;\r
37 assign wb_int_o = 1'b0;\r
38 assign wb_dat_o = data_reg;\r
39\r
40endmodule\r
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