we_o
[raggedstone] / dhwk_old / source / top_dhwk.vhd
CommitLineData
ebba63a9 1library ieee;\r
2use ieee.std_logic_1164.all;\r
3use ieee.std_logic_arith.all;\r
4use ieee.std_logic_unsigned.all;\r
5\r
ebba63a9 6entity dhwk is\r
7port (\r
8\r
9 -- General \r
10 PCI_CLK : in std_logic;\r
11 PCI_nRES : in std_logic;\r
12 \r
13 -- PCI target 32bits\r
14 PCI_AD : inout std_logic_vector(31 downto 0);\r
15 PCI_CBE : in std_logic_vector(3 downto 0);\r
16 PCI_PAR : out std_logic; \r
17 PCI_nFRAME : in std_logic;\r
18 PCI_nIRDY : in std_logic;\r
19 PCI_nTRDY : out std_logic;\r
20 PCI_nDEVSEL : out std_logic;\r
21 PCI_nSTOP : out std_logic;\r
22 PCI_IDSEL : in std_logic;\r
23 PCI_nPERR : out std_logic;\r
24 PCI_nSERR : out std_logic;\r
25 PCI_nINT : out std_logic;\r
26 \r
27 -- debug signals\r
28 LED3 : out std_logic;\r
29 LED2 : out std_logic;\r
30 LED4 : out std_logic;\r
31 LED5 : out std_logic\r
32\r
33);\r
34end dhwk;\r
35\r
36\r
ebba63a9 37architecture dhwk_arch of dhwk is\r
38\r
39\r
ebba63a9 40component pci32tlite\r
41port (\r
42\r
43 -- General \r
44 clk33 : in std_logic;\r
45 nrst : in std_logic;\r
46 \r
47 -- PCI target 32bits\r
48 ad : inout std_logic_vector(31 downto 0);\r
49 cbe : in std_logic_vector(3 downto 0);\r
50 par : out std_logic; \r
51 frame : in std_logic;\r
52 irdy : in std_logic;\r
53 trdy : out std_logic;\r
54 devsel : out std_logic;\r
55 stop : out std_logic;\r
56 idsel : in std_logic;\r
57 perr : out std_logic;\r
58 serr : out std_logic;\r
59 intb : out std_logic;\r
60 \r
61 -- Master whisbone\r
62 wb_adr_o : out std_logic_vector(24 downto 1); \r
63 wb_dat_i : in std_logic_vector(15 downto 0);\r
64 wb_dat_o : out std_logic_vector(15 downto 0);\r
65 wb_sel_o : out std_logic_vector(1 downto 0);\r
66 wb_we_o : out std_logic;\r
67 wb_stb_o : out std_logic;\r
68 wb_cyc_o : out std_logic;\r
69 wb_ack_i : in std_logic;\r
70 wb_err_i : in std_logic;\r
71 wb_int_i : in std_logic;\r
72\r
73 -- debug signals\r
74 debug_init : out std_logic;\r
75 debug_access : out std_logic \r
76\r
77 );\r
78end component;\r
79\r
80component heartbeat\r
81port (\r
82 clk_i : in std_logic;\r
83 nrst_i : in std_logic;\r
84 led2_o : out std_logic;\r
85 led3_o : out std_logic;\r
86 led4_o : out std_logic;\r
87 led5_o : out std_logic\r
88);\r
89end component;\r
90\r
7b50ad38 91component generic_fifo_sc_a\r
92port (\r
93 clk : in std_logic;\r
94 rst : in std_logic;\r
95 clr : in std_logic;\r
96 din : in std_logic_vector(7 downto 0);\r
97 we : in std_logic;\r
98 dout : out std_logic_vector(7 downto 0);\r
99 re : in std_logic;\r
100 full : out std_logic;\r
101 full_r : out std_logic;\r
102 empty : out std_logic;\r
103 empty_r : out std_logic;\r
104 full_n : out std_logic;\r
105 full_n_r : out std_logic;\r
106 empty_n : out std_logic;\r
107 empty_n_r : out std_logic;\r
108 level : out std_logic_vector(1 downto 0)\r
109);\r
110end component;\r
111\r
b125f15f 112component wb_fifo\r
2d8e1276 113port (\r
114 clk_i : in std_logic;\r
115 nrst_i : in std_logic;\r
116 \r
117 wb_adr_i : in std_logic_vector(24 downto 1);\r
118 wb_dat_o : out std_logic_vector(15 downto 0);\r
119 wb_dat_i : in std_logic_vector(15 downto 0);\r
120 wb_sel_i : in std_logic_vector(1 downto 0);\r
121 wb_we_i : in std_logic;\r
122 wb_stb_i : in std_logic;\r
123 wb_cyc_i : in std_logic;\r
124 wb_ack_o : out std_logic;\r
125 wb_err_o : out std_logic;\r
126 wb_int_o : out std_logic;\r
127 \r
b125f15f 128 fifo_data_i : in std_logic_vector(7 downto 0);\r
7e85e648 129 fifo_data_o : out std_logic_vector(7 downto 0);\r
b125f15f 130\r
8fe28453 131 fifo_we_o : out std_logic;\r
132 fifo_re_o : out std_logic\r
2d8e1276 133);\r
134end component;\r
135\r
ec7a1296 136signal wb_adr : std_logic_vector(24 downto 1); \r
137signal wb_dat_out : std_logic_vector(15 downto 0);\r
138signal wb_dat_in : std_logic_vector(15 downto 0);\r
139signal wb_sel : std_logic_vector(1 downto 0);\r
140signal wb_we : std_logic;\r
141signal wb_stb : std_logic;\r
142signal wb_cyc : std_logic;\r
143signal wb_ack : std_logic;\r
144signal wb_err : std_logic;\r
145signal wb_int : std_logic;\r
ebba63a9 146\r
fe5730c7 147signal fifo_din : std_logic_vector(7 downto 0);\r
148signal fifo_dout : std_logic_vector(7 downto 0);\r
149signal fifo_we : std_logic;\r
150signal fifo_re : std_logic;\r
151\r
152\r
ebba63a9 153\r
154begin\r
155\r
ebba63a9 156u_pci: component pci32tlite\r
157port map(\r
158 clk33 => PCI_CLK,\r
159 nrst => PCI_nRES,\r
160 ad => PCI_AD,\r
161 cbe => PCI_CBE,\r
162 par => PCI_PAR,\r
163 frame => PCI_nFRAME,\r
164 irdy => PCI_nIRDY,\r
165 trdy => PCI_nTRDY,\r
166 devsel => PCI_nDEVSEL,\r
167 stop => PCI_nSTOP,\r
168 idsel => PCI_IDSEL,\r
169 perr => PCI_nPERR,\r
170 serr => PCI_nSERR,\r
171 intb => PCI_nINT,\r
172 wb_adr_o => wb_adr, \r
173 wb_dat_i => wb_dat_out,\r
174 wb_dat_o => wb_dat_in,\r
175 wb_sel_o => wb_sel, \r
176 wb_we_o => wb_we,\r
177 wb_stb_o => wb_stb, \r
178 wb_cyc_o => wb_cyc,\r
179 wb_ack_i => wb_ack,\r
180 wb_err_i => wb_err,\r
181 wb_int_i => wb_int\r
182-- debug_init => LED3,\r
183-- debug_access => LED2\r
fe5730c7 184);\r
185\r
186my_generic_fifo: component generic_fifo_sc_a\r
187port map(\r
188 clk => PCI_CLK,\r
189 rst => PCI_nRES,\r
b73dc457 190 clr => '0',\r
fe5730c7 191 din => fifo_din,\r
192 we => fifo_we,\r
193 dout => fifo_dout,\r
194 re => fifo_re\r
195-- full => ,\r
196-- full_r => ,\r
197-- empty => ,\r
198-- empty_r => ,\r
199-- full_n => ,\r
200-- full_n_r => ,\r
201-- empty_n => ,\r
202-- empty_n_r => ,\r
203-- level => ,\r
204);\r
205\r
206my_fifo: component wb_fifo\r
207port map(\r
208 clk_i => PCI_CLK,\r
209 nrst_i => PCI_nRES,\r
210\r
211 wb_adr_i => wb_adr,\r
212 wb_dat_o => wb_dat_out,\r
213 wb_dat_i => wb_dat_in,\r
214 wb_sel_i => wb_sel,\r
215 wb_we_i => wb_we,\r
216 wb_stb_i => wb_stb,\r
217 wb_cyc_i => wb_cyc,\r
218 wb_ack_o => wb_ack,\r
219 wb_err_o => wb_err,\r
220 wb_int_o => wb_int,\r
221\r
222 fifo_data_i => fifo_dout,\r
223 fifo_data_o => fifo_din,\r
224\r
8fe28453 225 fifo_we_o => fifo_we,\r
226 fifo_re_o => fifo_re\r
fe5730c7 227);\r
ebba63a9 228\r
ebba63a9 229my_heartbeat: component heartbeat\r
230port map( \r
231 clk_i => PCI_CLK,\r
232 nrst_i => PCI_nRES,\r
233 led2_o => LED2,\r
234 led3_o => LED3,\r
235 led4_o => LED4,\r
236 led5_o => LED5\r
237);\r
238\r
239end dhwk_arch;\r
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