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40a1f26c | 1 | ////////////////////////////////////////////////////////////////////// |
2 | //// //// | |
3 | //// eth_clockgen.v //// | |
4 | //// //// | |
5 | //// This file is part of the Ethernet IP core project //// | |
6 | //// http://www.opencores.org/projects/ethmac/ //// | |
7 | //// //// | |
8 | //// Author(s): //// | |
9 | //// - Igor Mohor (igorM@opencores.org) //// | |
10 | //// //// | |
11 | //// All additional information is avaliable in the Readme.txt //// | |
12 | //// file. //// | |
13 | //// //// | |
14 | ////////////////////////////////////////////////////////////////////// | |
15 | //// //// | |
16 | //// Copyright (C) 2001 Authors //// | |
17 | //// //// | |
18 | //// This source file may be used and distributed without //// | |
19 | //// restriction provided that this copyright statement is not //// | |
20 | //// removed from the file and that any derivative work contains //// | |
21 | //// the original copyright notice and the associated disclaimer. //// | |
22 | //// //// | |
23 | //// This source file is free software; you can redistribute it //// | |
24 | //// and/or modify it under the terms of the GNU Lesser General //// | |
25 | //// Public License as published by the Free Software Foundation; //// | |
26 | //// either version 2.1 of the License, or (at your option) any //// | |
27 | //// later version. //// | |
28 | //// //// | |
29 | //// This source is distributed in the hope that it will be //// | |
30 | //// useful, but WITHOUT ANY WARRANTY; without even the implied //// | |
31 | //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// | |
32 | //// PURPOSE. See the GNU Lesser General Public License for more //// | |
33 | //// details. //// | |
34 | //// //// | |
35 | //// You should have received a copy of the GNU Lesser General //// | |
36 | //// Public License along with this source; if not, download it //// | |
37 | //// from http://www.opencores.org/lgpl.shtml //// | |
38 | //// //// | |
39 | ////////////////////////////////////////////////////////////////////// | |
40 | // | |
41 | // CVS Revision History | |
42 | // | |
43 | // $Log: eth_clockgen.v,v $ | |
44 | // Revision 1.1 2007-03-20 17:50:56 sithglan | |
45 | // add shit | |
46 | // | |
47 | // Revision 1.4 2005/02/21 12:48:05 igorm | |
48 | // Warning fixes. | |
49 | // | |
50 | // Revision 1.3 2002/01/23 10:28:16 mohor | |
51 | // Link in the header changed. | |
52 | // | |
53 | // Revision 1.2 2001/10/19 08:43:51 mohor | |
54 | // eth_timescale.v changed to timescale.v This is done because of the | |
55 | // simulation of the few cores in a one joined project. | |
56 | // | |
57 | // Revision 1.1 2001/08/06 14:44:29 mohor | |
58 | // A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex). | |
59 | // Include files fixed to contain no path. | |
60 | // File names and module names changed ta have a eth_ prologue in the name. | |
61 | // File eth_timescale.v is used to define timescale | |
62 | // All pin names on the top module are changed to contain _I, _O or _OE at the end. | |
63 | // Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O | |
64 | // and Mdo_OE. The bidirectional signal must be created on the top level. This | |
65 | // is done due to the ASIC tools. | |
66 | // | |
67 | // Revision 1.1 2001/07/30 21:23:42 mohor | |
68 | // Directory structure changed. Files checked and joind together. | |
69 | // | |
70 | // Revision 1.3 2001/06/01 22:28:55 mohor | |
71 | // This files (MIIM) are fully working. They were thoroughly tested. The testbench is not updated. | |
72 | // | |
73 | // | |
74 | ||
75 | `include "timescale.v" | |
76 | ||
77 | module eth_clockgen(Clk, Reset, Divider, MdcEn, MdcEn_n, Mdc); | |
78 | ||
79 | parameter Tp=1; | |
80 | ||
81 | input Clk; // Input clock (Host clock) | |
82 | input Reset; // Reset signal | |
83 | input [7:0] Divider; // Divider (input clock will be divided by the Divider[7:0]) | |
84 | ||
85 | output Mdc; // Output clock | |
86 | output MdcEn; // Enable signal is asserted for one Clk period before Mdc rises. | |
87 | output MdcEn_n; // Enable signal is asserted for one Clk period before Mdc falls. | |
88 | ||
89 | reg Mdc; | |
90 | reg [7:0] Counter; | |
91 | ||
92 | wire CountEq0; | |
93 | wire [7:0] CounterPreset; | |
94 | wire [7:0] TempDivider; | |
95 | ||
96 | ||
97 | assign TempDivider[7:0] = (Divider[7:0]<2)? 8'h02 : Divider[7:0]; // If smaller than 2 | |
98 | assign CounterPreset[7:0] = (TempDivider[7:0]>>1) - 1'b1; // We are counting half of period | |
99 | ||
100 | ||
101 | // Counter counts half period | |
102 | always @ (posedge Clk or posedge Reset) | |
103 | begin | |
104 | if(Reset) | |
105 | Counter[7:0] <= #Tp 8'h1; | |
106 | else | |
107 | begin | |
108 | if(CountEq0) | |
109 | begin | |
110 | Counter[7:0] <= #Tp CounterPreset[7:0]; | |
111 | end | |
112 | else | |
113 | Counter[7:0] <= #Tp Counter - 8'h1; | |
114 | end | |
115 | end | |
116 | ||
117 | ||
118 | // Mdc is asserted every other half period | |
119 | always @ (posedge Clk or posedge Reset) | |
120 | begin | |
121 | if(Reset) | |
122 | Mdc <= #Tp 1'b0; | |
123 | else | |
124 | begin | |
125 | if(CountEq0) | |
126 | Mdc <= #Tp ~Mdc; | |
127 | end | |
128 | end | |
129 | ||
130 | ||
131 | assign CountEq0 = Counter == 8'h0; | |
132 | assign MdcEn = CountEq0 & ~Mdc; | |
133 | assign MdcEn_n = CountEq0 & Mdc; | |
134 | ||
135 | endmodule | |
136 | ||
137 |