[raggedstone] / ethernet / source / ethernet / eth_fifo.v

//////////////////////////////////////////////////////////////////////
////                                                              ////
////  eth_fifo.v                                                  ////
////                                                              ////
////  This file is part of the Ethernet IP core project           ////
////  http://www.opencores.org/projects/ethmac/                   ////
////                                                              ////
////  Author(s):                                                  ////
////      - Igor Mohor (igorM@opencores.org)                      ////
////                                                              ////
////  All additional information is avaliable in the Readme.txt   ////
////  file.                                                       ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2001 Authors                                   ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: eth_fifo.v,v $
// Revision 1.1  2007-03-20 17:50:56  sithglan
// add shit
//
// Revision 1.4  2005/02/21 12:48:07  igorm
// Warning fixes.
//
// Revision 1.3  2002/04/22 13:45:52  mohor
// Generic ram or Xilinx ram can be used in fifo (selectable by setting
// ETH_FIFO_XILINX in eth_defines.v).
//
// Revision 1.2  2002/03/25 13:33:04  mohor
// When clear and read/write are active at the same time, cnt and pointers are
// set to 1.
//
// Revision 1.1  2002/02/05 16:44:39  mohor
// Both rx and tx part are finished. Tested with wb_clk_i between 10 and 200
// MHz. Statuses, overrun, control frame transmission and reception still  need
// to be fixed.
//
//

`include "eth_defines.v"
`include "timescale.v"

module eth_fifo (data_in, data_out, clk, reset, write, read, clear, almost_full, full, almost_empty, empty, cnt);

parameter DATA_WIDTH    = 32;
parameter DEPTH         = 8;
parameter CNT_WIDTH     = 4;

parameter Tp            = 1;

input                     clk;
input                     reset;
input                     write;
input                     read;
input                     clear;
input   [DATA_WIDTH-1:0]  data_in;

output  [DATA_WIDTH-1:0]  data_out;
output                    almost_full;
output                    full;
output                    almost_empty;
output                    empty;
output  [CNT_WIDTH-1:0]   cnt;

`ifdef ETH_FIFO_XILINX
`else
  `ifdef ETH_ALTERA_ALTSYNCRAM
  `else
    reg     [DATA_WIDTH-1:0]  fifo  [0:DEPTH-1];
    reg     [DATA_WIDTH-1:0]  data_out;
  `endif
`endif

reg     [CNT_WIDTH-1:0]   cnt;
reg     [CNT_WIDTH-2:0]   read_pointer;
reg     [CNT_WIDTH-2:0]   write_pointer;


always @ (posedge clk or posedge reset)
begin
  if(reset)
    cnt <=#Tp 0;
  else
  if(clear)
    cnt <=#Tp { {(CNT_WIDTH-1){1'b0}}, read^write};
  else
  if(read ^ write)
    if(read)
      cnt <=#Tp cnt - 1'b1;
    else
      cnt <=#Tp cnt + 1'b1;
end

always @ (posedge clk or posedge reset)
begin
  if(reset)
    read_pointer <=#Tp 0;
  else
  if(clear)
    read_pointer <=#Tp { {(CNT_WIDTH-2){1'b0}}, read};
  else
  if(read & ~empty)
    read_pointer <=#Tp read_pointer + 1'b1;
end

always @ (posedge clk or posedge reset)
begin
  if(reset)
    write_pointer <=#Tp 0;
  else
  if(clear)
    write_pointer <=#Tp { {(CNT_WIDTH-2){1'b0}}, write};
  else
  if(write & ~full)
    write_pointer <=#Tp write_pointer + 1'b1;
end

assign empty = ~(|cnt);
assign almost_empty = cnt == 1;
assign full  = cnt == DEPTH;
assign almost_full  = &cnt[CNT_WIDTH-2:0];


`ifdef ETH_FIFO_XILINX
  xilinx_dist_ram_16x32 fifo
  ( .data_out(data_out), 
    .we(write & ~full),
    .data_in(data_in),
    .read_address( clear ? {CNT_WIDTH-1{1'b0}} : read_pointer),
    .write_address(clear ? {CNT_WIDTH-1{1'b0}} : write_pointer),
    .wclk(clk)
  );
`else   // !ETH_FIFO_XILINX
`ifdef ETH_ALTERA_ALTSYNCRAM
  altera_dpram_16x32	altera_dpram_16x32_inst
  (\r
  	.data             (data_in),\r
  	.wren             (write & ~full),\r
  	.wraddress        (clear ? {CNT_WIDTH-1{1'b0}} : write_pointer),\r
  	.rdaddress        (clear ? {CNT_WIDTH-1{1'b0}} : read_pointer ),\r
  	.clock            (clk),\r
  	.q                (data_out)\r
  );  //exemplar attribute altera_dpram_16x32_inst NOOPT TRUE\r
`else   // !ETH_ALTERA_ALTSYNCRAM
  always @ (posedge clk)
  begin
    if(write & clear)
      fifo[0] <=#Tp data_in;
    else
   if(write & ~full)
      fifo[write_pointer] <=#Tp data_in;
  end
  

  always @ (posedge clk)
  begin
    if(clear)
      data_out <=#Tp fifo[0];
    else
      data_out <=#Tp fifo[read_pointer];
  end
`endif  // !ETH_ALTERA_ALTSYNCRAM
`endif  // !ETH_FIFO_XILINX


endmodule
Commit	Line	Data
40a1f26c	1	//////////////////////////////////////////////////////////////////////
	2	//// ////
	3	//// eth_fifo.v ////
	4	//// ////
	5	//// This file is part of the Ethernet IP core project ////
	6	//// http://www.opencores.org/projects/ethmac/ ////
	7	//// ////
	8	//// Author(s): ////
	9	//// - Igor Mohor (igorM@opencores.org) ////
	10	//// ////
	11	//// All additional information is avaliable in the Readme.txt ////
	12	//// file. ////
	13	//// ////
	14	//////////////////////////////////////////////////////////////////////
	15	//// ////
	16	//// Copyright (C) 2001 Authors ////
	17	//// ////
	18	//// This source file may be used and distributed without ////
	19	//// restriction provided that this copyright statement is not ////
	20	//// removed from the file and that any derivative work contains ////
	21	//// the original copyright notice and the associated disclaimer. ////
	22	//// ////
	23	//// This source file is free software; you can redistribute it ////
	24	//// and/or modify it under the terms of the GNU Lesser General ////
	25	//// Public License as published by the Free Software Foundation; ////
	26	//// either version 2.1 of the License, or (at your option) any ////
	27	//// later version. ////
	28	//// ////
	29	//// This source is distributed in the hope that it will be ////
	30	//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
	31	//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
	32	//// PURPOSE. See the GNU Lesser General Public License for more ////
	33	//// details. ////
	34	//// ////
	35	//// You should have received a copy of the GNU Lesser General ////
	36	//// Public License along with this source; if not, download it ////
	37	//// from http://www.opencores.org/lgpl.shtml ////
	38	//// ////
	39	//////////////////////////////////////////////////////////////////////
	40	//
	41	// CVS Revision History
	42	//
	43	// $Log: eth_fifo.v,v $
	44	// Revision 1.1 2007-03-20 17:50:56 sithglan
	45	// add shit
	46	//
	47	// Revision 1.4 2005/02/21 12:48:07 igorm
	48	// Warning fixes.
	49	//
	50	// Revision 1.3 2002/04/22 13:45:52 mohor
	51	// Generic ram or Xilinx ram can be used in fifo (selectable by setting
	52	// ETH_FIFO_XILINX in eth_defines.v).
	53	//
	54	// Revision 1.2 2002/03/25 13:33:04 mohor
	55	// When clear and read/write are active at the same time, cnt and pointers are
	56	// set to 1.
	57	//
	58	// Revision 1.1 2002/02/05 16:44:39 mohor
	59	// Both rx and tx part are finished. Tested with wb_clk_i between 10 and 200
	60	// MHz. Statuses, overrun, control frame transmission and reception still need
	61	// to be fixed.
	62	//
	63	//
	64
65	`include "eth_defines.v"
66	`include "timescale.v"
67
68	module eth_fifo (data_in, data_out, clk, reset, write, read, clear, almost_full, full, almost_empty, empty, cnt);
69
70	parameter DATA_WIDTH = 32;
71	parameter DEPTH = 8;
72	parameter CNT_WIDTH = 4;
73
74	parameter Tp = 1;
75
76	input clk;
77	input reset;
78	input write;
79	input read;
80	input clear;
81	input [DATA_WIDTH-1:0] data_in;
82
83	output [DATA_WIDTH-1:0] data_out;
84	output almost_full;
85	output full;
86	output almost_empty;
87	output empty;
88	output [CNT_WIDTH-1:0] cnt;
89
90	`ifdef ETH_FIFO_XILINX
91	`else
92	`ifdef ETH_ALTERA_ALTSYNCRAM
93	`else
94	reg [DATA_WIDTH-1:0] fifo [0:DEPTH-1];
95	reg [DATA_WIDTH-1:0] data_out;
96	`endif
97	`endif
98
99	reg [CNT_WIDTH-1:0] cnt;
100	reg [CNT_WIDTH-2:0] read_pointer;
101	reg [CNT_WIDTH-2:0] write_pointer;
102
103
104	always @ (posedge clk or posedge reset)
105	begin
106	if(reset)
107	cnt <=#Tp 0;
108	else
109	if(clear)
110	cnt <=#Tp { {(CNT_WIDTH-1){1'b0}}, read^write};
111	else
112	if(read ^ write)
113	if(read)
114	cnt <=#Tp cnt - 1'b1;
115	else
116	cnt <=#Tp cnt + 1'b1;
117	end
118
119	always @ (posedge clk or posedge reset)
120	begin
121	if(reset)
122	read_pointer <=#Tp 0;
123	else
124	if(clear)
125	read_pointer <=#Tp { {(CNT_WIDTH-2){1'b0}}, read};
126	else
127	if(read & ~empty)
128	read_pointer <=#Tp read_pointer + 1'b1;
129	end
130
131	always @ (posedge clk or posedge reset)
132	begin
133	if(reset)
134	write_pointer <=#Tp 0;
135	else
136	if(clear)
137	write_pointer <=#Tp { {(CNT_WIDTH-2){1'b0}}, write};
138	else
139	if(write & ~full)
140	write_pointer <=#Tp write_pointer + 1'b1;
141	end
142
143	assign empty = ~(\|cnt);
144	assign almost_empty = cnt == 1;
145	assign full = cnt == DEPTH;
146	assign almost_full = &cnt[CNT_WIDTH-2:0];
147
148
149
150	`ifdef ETH_FIFO_XILINX
151	xilinx_dist_ram_16x32 fifo
152	( .data_out(data_out),
153	.we(write & ~full),
154	.data_in(data_in),
155	.read_address( clear ? {CNT_WIDTH-1{1'b0}} : read_pointer),
156	.write_address(clear ? {CNT_WIDTH-1{1'b0}} : write_pointer),
157	.wclk(clk)
158	);
159	`else // !ETH_FIFO_XILINX
160	`ifdef ETH_ALTERA_ALTSYNCRAM
161	altera_dpram_16x32 altera_dpram_16x32_inst
162	(\r
163	.data (data_in),\r
164	.wren (write & ~full),\r
165	.wraddress (clear ? {CNT_WIDTH-1{1'b0}} : write_pointer),\r
166	.rdaddress (clear ? {CNT_WIDTH-1{1'b0}} : read_pointer ),\r
167	.clock (clk),\r
168	.q (data_out)\r
169	); //exemplar attribute altera_dpram_16x32_inst NOOPT TRUE\r
170	`else // !ETH_ALTERA_ALTSYNCRAM
171	always @ (posedge clk)
172	begin
173	if(write & clear)
174	fifo[0] <=#Tp data_in;
175	else
176	if(write & ~full)
177	fifo[write_pointer] <=#Tp data_in;
178	end
179
180
181	always @ (posedge clk)
182	begin
183	if(clear)
184	data_out <=#Tp fifo[0];
185	else
186	data_out <=#Tp fifo[read_pointer];
187	end
188	`endif // !ETH_ALTERA_ALTSYNCRAM
189	`endif // !ETH_FIFO_XILINX
190
191
192	endmodule