white space; fixme
[raggedstone] / heartbeat / source / wb_7seg.v
CommitLineData
95764a11 1module wb_7seg_new (clk_i, nrst_i, wb_adr_i, wb_dat_o, wb_dat_i, wb_sel_i, wb_we_i, \r
2 wb_stb_i, wb_cyc_i, wb_ack_o, wb_err_o, wb_int_o, DISP_SEL, DISP_LED);\r
3\r
4 input clk_i;\r
5 input nrst_i;\r
6 input [24:1] wb_adr_i;\r
7 output [15:0] wb_dat_o;\r
8 input [15:0] wb_dat_i;\r
9 input [1:0] wb_sel_i;\r
10 input wb_we_i;\r
11 input wb_stb_i;\r
12 input wb_cyc_i;\r
13 output wb_ack_o;\r
14 output wb_err_o;\r
15 output wb_int_o;\r
16 output reg [3:0] DISP_SEL;\r
17 output reg [6:0] DISP_LED;\r
18\r
19 reg [15:0] data_reg;\r
20 reg [6:0] disp_cnt;\r
21 reg [3:0] disp_data;\r
22 wire [6:0] disp_data_led;\r
23 reg [3:0] disp_pos;\r
24\r
25 always @(posedge clk_i or negedge nrst_i)\r
26 begin\r
27 if (nrst_i == 0)\r
28 data_reg <= 16'hABCD;\r
29 else \r
30 if (wb_stb_i && wb_we_i)\r
31 data_reg <= wb_dat_i;\r
32 end\r
33\r
34 assign wb_ack_o = wb_stb_i;\r
35 assign wb_err_o = 1'b0;\r
36 assign wb_int_o = 1'b0;\r
37 assign wb_dat_o = data_reg;\r
38\r
39 always @(posedge clk_i or negedge nrst_i)\r
40 begin\r
41 if (nrst_i == 0)\r
42 disp_cnt <= 7'b0000000;\r
43 else \r
44 disp_cnt <= disp_cnt + 1;\r
45 end\r
46\r
47 always @(posedge clk_i or negedge nrst_i)\r
48 begin\r
49 if (nrst_i == 0)\r
50 disp_pos <= 4'b0010;\r
51 else \r
52 if (disp_cnt == 7'b1111111)\r
53 disp_pos <= {DISP_SEL[2] , DISP_SEL[1] , DISP_SEL[0] , DISP_SEL[3]};\r
54 end\r
55\r
56 always @(posedge clk_i or negedge nrst_i)\r
57 begin\r
58 if (nrst_i == 0)\r
59 disp_data <= 4'b0000;\r
60 else \r
61 case (DISP_SEL)\r
62 4'b1000: disp_data <= data_reg[3:0];\r
63 4'b0100: disp_data <= data_reg[7:4];\r
64 4'b0010: disp_data <= data_reg[11:8];\r
65 4'b0001: disp_data <= data_reg[15:12];\r
66 endcase\r
67 end\r
68\r
69 disp_dec u0 (disp_data, disp_data_led);\r
70\r
71 always @(posedge clk_i or negedge nrst_i)\r
72 begin\r
73 if (nrst_i == 0)\r
74 DISP_LED <= 7'b0000000;\r
75 else \r
76 DISP_LED <= disp_data_led;\r
77 end\r
78\r
79 always @(posedge clk_i or negedge nrst_i)\r
80 begin\r
81 if (nrst_i == 0)\r
82 DISP_SEL <= 0;\r
83 else \r
84 DISP_SEL <= disp_pos;\r
85 end\r
86\r
87endmodule\r
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