[raggedstone] / dhwk / source / config_3Ch.vhd

-- J.STELZNER\r
-- INFORMATIK-3 LABOR\r
-- 23.08.2006\r
-- File: CONFIG_3CH.VHD\r
\r
library IEEE;\r
use IEEE.std_logic_1164.all;\r
\r
entity CONFIG_3CH is\r
        port (\r
                PCI_CLOCK	:in std_logic;\r
                PCI_RSTn	:in std_logic;\r
                AD_REG		:in std_logic_vector (31 downto 0);\r
                CBE_REGn	:in std_logic_vector ( 3 downto 0);\r
                CONF_WR_3CH	:in std_logic;\r
                CONF_DATA_3CH	:out std_logic_vector (31 downto 0)\r
        );\r
end entity CONFIG_3CH;\r
\r
architecture CONFIG_3CH_DESIGN of CONFIG_3CH is\r
\r
-- PCI Configuration Space Header Addr : HEX 3C --\r
\r
	signal CONF_MAX_LAT :std_logic_vector (31 downto 24);\r
	signal CONF_MIN_GNT :std_logic_vector (23 downto 16);  \r
	signal CONF_INT_PIN :std_logic_vector (15 downto  8);\r
	signal CONF_INT_LINE :std_logic_vector ( 7 downto  0);  \r
\r
	constant cmd_conf_write :std_logic_vector(3 downto 0) := "1011";\r
begin \r
\r
--*******************************************************************\r
--*********** PCI Configuration Space Header "INTERRUPT" ************\r
--*******************************************************************\r
\r
		CONF_MAX_LAT	<= X"00";\r
		CONF_MIN_GNT	<= X"00";\r
--	CONF_INT_PIN	<= X"00";				-- Interrupt -\r
		CONF_INT_PIN	<= X"01";				-- Interrupt A\r
--	CONF_INT_PIN	<= X"02";				-- Interrupt B\r
--	CONF_INT_PIN	<= X"03";				-- Interrupt C \r
--	CONF_INT_PIN	<= X"04";				-- Interrupt D\r
--	CONF_INT_PIN	<= X"05 - FF0";	-- Reserviert\r
\r
process (PCI_CLOCK,PCI_RSTn) \r
begin\r
        if PCI_RSTn = '0' then\r
                CONF_INT_LINE <= (others => '0');\r
\r
        elsif (PCI_CLOCK'event and PCI_CLOCK = '1') then\r
                if CONF_WR_3CH = '1'and CBE_REGn(0) = '0' then \r
                        CONF_INT_LINE(7 downto 0) <= AD_REG(7 downto 0);\r
                end if;\r
        end if;\r
end process;\r
\r
CONF_DATA_3CH	<= CONF_MAX_LAT & CONF_MIN_GNT & CONF_INT_PIN & CONF_INT_LINE;\r
\r
end architecture CONFIG_3CH_DESIGN;\r
Commit	Line	Data
377c0242	1	-- J.STELZNER\r
	2	-- INFORMATIK-3 LABOR\r
	3	-- 23.08.2006\r
	4	-- File: CONFIG_3CH.VHD\r
	5	\r
	6	library IEEE;\r
	7	use IEEE.std_logic_1164.all;\r
	8	\r
	9	entity CONFIG_3CH is\r
d6816134	10	port (\r
	11	PCI_CLOCK :in std_logic;\r
	12	PCI_RSTn :in std_logic;\r
	13	AD_REG :in std_logic_vector (31 downto 0);\r
	14	CBE_REGn :in std_logic_vector ( 3 downto 0);\r
	15	CONF_WR_3CH :in std_logic;\r
	16	CONF_DATA_3CH :out std_logic_vector (31 downto 0)\r
	17	);\r
377c0242	18	end entity CONFIG_3CH;\r
	19	\r
	20	architecture CONFIG_3CH_DESIGN of CONFIG_3CH is\r
	21	\r
	22	-- PCI Configuration Space Header Addr : HEX 3C --\r
	23	\r
d6816134	24	signal CONF_MAX_LAT :std_logic_vector (31 downto 24);\r
	25	signal CONF_MIN_GNT :std_logic_vector (23 downto 16); \r
	26	signal CONF_INT_PIN :std_logic_vector (15 downto 8);\r
	27	signal CONF_INT_LINE :std_logic_vector ( 7 downto 0); \r
1cc8dbeb	28	\r
d6816134	29	constant cmd_conf_write :std_logic_vector(3 downto 0) := "1011";\r
377c0242	30	begin \r
	31	\r
	32	--*******************************************************************\r
	33	--********* PCI Configuration Space Header "INTERRUPT" **********\r
	34	--*******************************************************************\r
	35	\r
	36	CONF_MAX_LAT <= X"00";\r
	37	CONF_MIN_GNT <= X"00";\r
	38	-- CONF_INT_PIN <= X"00"; -- Interrupt -\r
	39	CONF_INT_PIN <= X"01"; -- Interrupt A\r
	40	-- CONF_INT_PIN <= X"02"; -- Interrupt B\r
	41	-- CONF_INT_PIN <= X"03"; -- Interrupt C \r
	42	-- CONF_INT_PIN <= X"04"; -- Interrupt D\r
	43	-- CONF_INT_PIN <= X"05 - FF0"; -- Reserviert\r
	44	\r
d6816134	45	process (PCI_CLOCK,PCI_RSTn) \r
	46	begin\r
	47	if PCI_RSTn = '0' then\r
	48	CONF_INT_LINE <= (others => '0');\r
377c0242	49	\r
d6816134	50	elsif (PCI_CLOCK'event and PCI_CLOCK = '1') then\r
	51	if CONF_WR_3CH = '1'and CBE_REGn(0) = '0' then \r
	52	CONF_INT_LINE(7 downto 0) <= AD_REG(7 downto 0);\r
	53	end if;\r
	54	end if;\r
	55	end process;\r
377c0242	56	\r
d6816134	57	CONF_DATA_3CH <= CONF_MAX_LAT & CONF_MIN_GNT & CONF_INT_PIN & CONF_INT_LINE;\r
377c0242	58	\r
377c0242	59	end architecture CONFIG_3CH_DESIGN;\r