]> git.zerfleddert.de Git - raggedstone/blame - dhwk/source/config_mux_0.vhd
trigger
[raggedstone] / dhwk / source / config_mux_0.vhd
CommitLineData
377c0242 1-- J.STELZNER\r
2-- INFORMATIK-3 LABOR\r
3-- 23.08.2006\r
4-- File: CONFIG_MUX_0.VHD\r
5\r
6library IEEE;\r
7use IEEE.std_logic_1164.all;\r
8\r
9entity CONFIG_MUX_0 is\r
10 port\r
11 (\r
12 READ_SEL :in std_logic_vector( 2 downto 0);\r
13 CONF_DATA_00H :in std_logic_vector(31 downto 0);\r
14 CONF_DATA_04H :in std_logic_vector(31 downto 0);\r
15 CONF_DATA_08H :in std_logic_vector(31 downto 0);\r
16 CONF_DATA_10H :in std_logic_vector(31 downto 0);\r
17 CONF_DATA_3CH :in std_logic_vector(31 downto 0);\r
18--CONF_DATA_40H :in std_logic_vector(31 downto 0);\r
19 CONF_DATA :out std_logic_vector(31 downto 0)\r
20 );\r
21end entity CONFIG_MUX_0;\r
22\r
23architecture CONFIG_MUX_0_DESIGN of CONFIG_MUX_0 is\r
24\r
25 signal MUX :std_logic_vector (31 downto 0); \r
26\r
27begin\r
28\r
29--*******************************************************************\r
30--******************* PCI Read Config-MUX **************************\r
31--*******************************************************************\r
32\r
33 MUX <= CONF_DATA_00H when READ_SEL <= "000" else \r
34 CONF_DATA_04H when READ_SEL <= "001" else\r
35 CONF_DATA_08H when READ_SEL <= "010" else\r
36 CONF_DATA_10H when READ_SEL <= "011" else\r
37 CONF_DATA_3CH when READ_SEL <= "100" else\r
38-- CONF_DATA_40H when READ_SEL <= "101" else\r
39 X"00000000" ;\r
40\r
41 CONF_DATA <= MUX ;\r
42\r
43\r
44end architecture CONFIG_MUX_0_DESIGN;\r
Impressum, Datenschutz