other watched signals
[raggedstone] / dhwk / source / fifo_control.vhd
CommitLineData
377c0242 1-- VHDL model created from schematic fifo_control.sch -- Jan 09 09:34:17 2007\r
2\r
3\r
4\r
5LIBRARY ieee;\r
6\r
7USE ieee.std_logic_1164.ALL;\r
8USE ieee.numeric_std.ALL;\r
9\r
10\r
11entity FIFO_CONTROL is\r
12 Port ( FIFO_RDn : In std_logic;\r
13 FLAG_IN_0 : In std_logic;\r
14 FLAG_IN_4 : In std_logic;\r
15 HOLD : In std_logic;\r
16 KONST_1 : In std_logic;\r
17 PCI_CLOCK : In std_logic;\r
18 PSC_ENABLE : In std_logic;\r
19 R_EFn : In std_logic;\r
20 R_FFn : In std_logic;\r
21 R_HFn : In std_logic;\r
22 RESET : In std_logic;\r
23 S_EFn : In std_logic;\r
24 S_FFn : In std_logic;\r
25 S_FIFO_Q_OUT : In std_logic_vector (7 downto 0);\r
26 S_HFn : In std_logic;\r
27 SERIAL_IN : In std_logic;\r
28 SPC_ENABLE : In std_logic;\r
29 SPC_RDY_IN : In std_logic;\r
30 WRITE_XX1_0 : In std_logic;\r
31 R_ERROR : Out std_logic;\r
32 R_FIFO_D_IN : Out std_logic_vector (7 downto 0);\r
33 R_FIFO_READn : Out std_logic;\r
34 R_FIFO_RESETn : Out std_logic;\r
35 R_FIFO_RETRANSMITn : Out std_logic;\r
36 R_FIFO_WRITEn : Out std_logic;\r
37 RESERVE : Out std_logic;\r
38 S_ERROR : Out std_logic;\r
39 S_FIFO_READn : Out std_logic;\r
40 S_FIFO_RESETn : Out std_logic;\r
41 S_FIFO_RETRANSMITn : Out std_logic;\r
42 S_FIFO_WRITEn : Out std_logic;\r
43 SERIAL_OUT : Out std_logic;\r
44 SPC_RDY_OUT : Out std_logic;\r
45 SR_ERROR : Out std_logic;\r
a76e12bd 46 SYNC_FLAG : Out std_logic_vector (7 downto 0);\r
47 PAR_SER_IN : Out std_logic_vector (7 downto 0));\r
377c0242 48end FIFO_CONTROL;\r
49\r
50architecture SCHEMATIC of FIFO_CONTROL is\r
51\r
52 SIGNAL gnd : std_logic := '0';\r
53 SIGNAL vcc : std_logic := '1';\r
54\r
55 signal XXXR_FIFO_WRITEn : std_logic;\r
56 signal XXXS_FIFO_READn : std_logic;\r
57 signal SYNC_FLAG_DUMMY : std_logic_vector (7 downto 0);\r
58 signal XXXR_FIFO_D_IN : std_logic_vector (7 downto 0);\r
59\r
60 component SER_PAR_CON\r
61 Port ( PCI_CLOCK : In std_logic;\r
62 RESET : In std_logic;\r
63 SERIAL_IN : In std_logic;\r
64 SPC_ENABLE : In std_logic;\r
65 SYNC_R_FIFO_FFn : In std_logic;\r
66 PAR_OUT : Out std_logic_vector (7 downto 0);\r
67 R_FIFO_WRITEn : Out std_logic;\r
68 SPC_RDY_OUT : Out std_logic );\r
69 end component;\r
70\r
71 component PAR_SER_CON\r
72 Port ( PAR_IN : In std_logic_vector (7 downto 0);\r
73 PCI_CLOCK : In std_logic;\r
74 PSC_ENABLE : In std_logic;\r
75 RESET : In std_logic;\r
76 SPC_RDY_IN : In std_logic;\r
77 SYNC_S_FIFO_EFn : In std_logic;\r
78 S_FIFO_READn : Out std_logic;\r
79 SER_OUT : Out std_logic );\r
80 end component;\r
81\r
82 component FIFO_IO_CONTROL\r
83 Port ( FIFO_RDn : In std_logic;\r
84 PCI_CLOCK : In std_logic;\r
85 RESET : In std_logic;\r
86 SYNC_FLAG_1 : In std_logic;\r
87 SYNC_FLAG_7 : In std_logic;\r
88 WRITE_XX1_0 : In std_logic;\r
89 R_ERROR : Out std_logic;\r
90 R_FIFO_READn : Out std_logic;\r
91 R_FIFO_RESETn : Out std_logic;\r
92 R_FIFO_RETRANSMITn : Out std_logic;\r
93 S_ERROR : Out std_logic;\r
94 S_FIFO_RESETn : Out std_logic;\r
95 S_FIFO_RETRANSMITn : Out std_logic;\r
96 S_FIFO_WRITEn : Out std_logic;\r
97 SR_ERROR : Out std_logic );\r
98 end component;\r
99\r
100 component CONNECTING_FSM\r
101 Port ( PCI_CLOCK : In std_logic;\r
102 PSC_ENABLE : In std_logic;\r
103 RESET : In std_logic;\r
104 S_FIFO_Q_OUT : In std_logic_vector (7 downto 0);\r
105 SPC_ENABLE : In std_logic;\r
106 SYNC_R_FIFO_FFn : In std_logic;\r
107 SYNC_S_FIFO_EFn : In std_logic;\r
108 R_FIFO_D_IN : Out std_logic_vector (7 downto 0);\r
109 R_FIFO_WRITEn : Out std_logic;\r
110 S_FIFO_READn : Out std_logic );\r
111 end component;\r
112\r
113 component FLAG_BUS\r
114 Port ( FLAG_IN_0 : In std_logic;\r
115 FLAG_IN_4 : In std_logic;\r
116 HOLD : In std_logic;\r
117 KONS_1 : In std_logic;\r
118 PCI_CLOCK : In std_logic;\r
119 R_EFn : In std_logic;\r
120 R_FFn : In std_logic;\r
121 R_HFn : In std_logic;\r
122 S_EFn : In std_logic;\r
123 S_FFn : In std_logic;\r
124 S_HFn : In std_logic;\r
125 SYNC_FLAG : Out std_logic_vector (7 downto 0) );\r
126 end component;\r
127\r
128begin\r
129\r
130 SYNC_FLAG <= SYNC_FLAG_DUMMY;\r
a76e12bd 131 PAR_SER_IN <= S_FIFO_Q_OUT;\r
132\r
377c0242 133\r
134 RESERVE <= gnd;\r
135 I23 : SER_PAR_CON\r
136 Port Map ( PCI_CLOCK=>PCI_CLOCK, RESET=>RESET,\r
137 SERIAL_IN=>SERIAL_IN, SPC_ENABLE=>SPC_ENABLE,\r
138 SYNC_R_FIFO_FFn=>SYNC_FLAG_DUMMY(3),\r
139 PAR_OUT(7 downto 0)=>R_FIFO_D_IN(7 downto 0),\r
140 R_FIFO_WRITEn=>R_FIFO_WRITEn, SPC_RDY_OUT=>SPC_RDY_OUT );\r
141 I22 : PAR_SER_CON\r
142 Port Map ( PAR_IN(7 downto 0)=>S_FIFO_Q_OUT(7 downto 0),\r
143 PCI_CLOCK=>PCI_CLOCK, PSC_ENABLE=>PSC_ENABLE,\r
144 RESET=>RESET, SPC_RDY_IN=>SPC_RDY_IN,\r
145 SYNC_S_FIFO_EFn=>SYNC_FLAG_DUMMY(5),\r
146 S_FIFO_READn=>S_FIFO_READn, SER_OUT=>SERIAL_OUT );\r
147 I21 : FIFO_IO_CONTROL\r
148 Port Map ( FIFO_RDn=>FIFO_RDn, PCI_CLOCK=>PCI_CLOCK, RESET=>RESET,\r
149 SYNC_FLAG_1=>SYNC_FLAG_DUMMY(1),\r
150 SYNC_FLAG_7=>SYNC_FLAG_DUMMY(7),\r
151 WRITE_XX1_0=>WRITE_XX1_0, R_ERROR=>R_ERROR,\r
152 R_FIFO_READn=>R_FIFO_READn,\r
153 R_FIFO_RESETn=>R_FIFO_RESETn,\r
154 R_FIFO_RETRANSMITn=>R_FIFO_RETRANSMITn,\r
155 S_ERROR=>S_ERROR, S_FIFO_RESETn=>S_FIFO_RESETn,\r
156 S_FIFO_RETRANSMITn=>S_FIFO_RETRANSMITn,\r
157 S_FIFO_WRITEn=>S_FIFO_WRITEn, SR_ERROR=>SR_ERROR );\r
158 I20 : CONNECTING_FSM\r
159 Port Map ( PCI_CLOCK=>PCI_CLOCK, PSC_ENABLE=>PSC_ENABLE,\r
160 RESET=>RESET,\r
161 S_FIFO_Q_OUT(7 downto 0)=>S_FIFO_Q_OUT(7 downto 0),\r
162 SPC_ENABLE=>SPC_ENABLE,\r
163 SYNC_R_FIFO_FFn=>SYNC_FLAG_DUMMY(3),\r
164 SYNC_S_FIFO_EFn=>SYNC_FLAG_DUMMY(5),\r
165 R_FIFO_D_IN(7 downto 0)=>XXXR_FIFO_D_IN(7 downto 0),\r
166 R_FIFO_WRITEn=>XXXR_FIFO_WRITEn,\r
167 S_FIFO_READn=>XXXS_FIFO_READn );\r
168 I19 : FLAG_BUS\r
169 Port Map ( FLAG_IN_0=>FLAG_IN_0, FLAG_IN_4=>FLAG_IN_4, HOLD=>HOLD,\r
170 KONS_1=>KONST_1, PCI_CLOCK=>PCI_CLOCK, R_EFn=>R_EFn,\r
171 R_FFn=>R_FFn, R_HFn=>R_HFn, S_EFn=>S_EFn, S_FFn=>S_FFn,\r
172 S_HFn=>S_HFn,\r
173 SYNC_FLAG(7 downto 0)=>SYNC_FLAG_DUMMY(7 downto 0) );\r
174\r
175end SCHEMATIC;\r
Impressum, Datenschutz