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[raggedstone] / ethernet / source / pci / pci_io_mux_ad_en_crit.v
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40a1f26c 1//////////////////////////////////////////////////////////////////////
2//// ////
3//// File name "pci_io_mux_ad_en_crit.v" ////
4//// ////
5//// This file is part of the "PCI bridge" project ////
6//// http://www.opencores.org/cores/pci/ ////
7//// ////
8//// Author(s): ////
9//// - Miha Dolenc (mihad@opencores.org) ////
10//// ////
11//// All additional information is avaliable in the README ////
12//// file. ////
13//// ////
14//// ////
15//////////////////////////////////////////////////////////////////////
16//// ////
17//// Copyright (C) 2001 Miha Dolenc, mihad@opencores.org ////
18//// ////
19//// This source file may be used and distributed without ////
20//// restriction provided that this copyright statement is not ////
21//// removed from the file and that any derivative work contains ////
22//// the original copyright notice and the associated disclaimer. ////
23//// ////
24//// This source file is free software; you can redistribute it ////
25//// and/or modify it under the terms of the GNU Lesser General ////
26//// Public License as published by the Free Software Foundation; ////
27//// either version 2.1 of the License, or (at your option) any ////
28//// later version. ////
29//// ////
30//// This source is distributed in the hope that it will be ////
31//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
32//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
33//// PURPOSE. See the GNU Lesser General Public License for more ////
34//// details. ////
35//// ////
36//// You should have received a copy of the GNU Lesser General ////
37//// Public License along with this source; if not, download it ////
38//// from http://www.opencores.org/lgpl.shtml ////
39//// ////
40//////////////////////////////////////////////////////////////////////
41//
42// CVS Revision History
43//
44// $Log: pci_io_mux_ad_en_crit.v,v $
45// Revision 1.1 2007-03-20 17:50:56 sithglan
46// add shit
47//
48// Revision 1.2 2003/01/27 16:49:31 mihad
49// Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed.
50//
51// Revision 1.1 2002/02/01 14:43:31 mihad
52// *** empty log message ***
53//
54//
55
56// module provides equation for ad output enables, which uses critical pci bus inputs
57
58// synopsys translate_off
59`include "timescale.v"
60// synopsys translate_on
61
62// module is provided for ad bus output enable Flip-Flops values
63module pci_io_mux_ad_en_crit
64(
65 ad_en_in,
66 pci_frame_in,
67 pci_trdy_in,
68 pci_stop_in,
69 ad_en_out
70);
71input ad_en_in,
72 pci_frame_in,
73 pci_trdy_in,
74 pci_stop_in ;
75output ad_en_out ;
76
77assign ad_en_out = ad_en_in && ( ~pci_frame_in || (pci_trdy_in && pci_stop_in) ) ;
78endmodule
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