27f6f620 |
1 | verilog work "source/ethernet/eth_crc.v" |
2 | verilog work "source/ethernet/eth_cop.v" |
3 | verilog work "source/ethernet/eth_maccontrol.v" |
4 | verilog work "source/ethernet/eth_register.v" |
5 | verilog work "source/ethernet/eth_fifo.v" |
6 | verilog work "source/ethernet/eth_rxstatem.v" |
7 | verilog work "source/ethernet/eth_txcounters.v" |
8 | verilog work "source/ethernet/eth_random.v" |
9 | verilog work "source/ethernet/eth_rxcounters.v" |
10 | verilog work "source/ethernet/eth_top.v" |
11 | verilog work "source/ethernet/eth_shiftreg.v" |
12 | verilog work "source/ethernet/eth_miim.v" |
13 | verilog work "source/ethernet/eth_wishbone.v" |
14 | verilog work "source/ethernet/eth_rxaddrcheck.v" |
15 | verilog work "source/ethernet/xilinx_dist_ram_16x32.v" |
16 | verilog work "source/ethernet/eth_spram_256x32.v" |
17 | verilog work "source/ethernet/eth_txethmac.v" |
18 | verilog work "source/ethernet/timescale.v" |
19 | verilog work "source/ethernet/eth_registers.v" |
20 | verilog work "source/ethernet/eth_defines.v" |
21 | verilog work "source/ethernet/eth_rxethmac.v" |
22 | verilog work "source/ethernet/eth_receivecontrol.v" |
23 | verilog work "source/ethernet/eth_outputcontrol.v" |
24 | verilog work "source/ethernet/eth_txstatem.v" |
25 | verilog work "source/ethernet/eth_transmitcontrol.v" |
26 | verilog work "source/ethernet/eth_macstatus.v" |
27 | verilog work "source/ethernet/eth_clockgen.v" |
28 | verilog work "source/pci/pci_target_unit.v" |
29 | verilog work "source/pci/pci_target32_stop_crit.v" |
30 | verilog work "source/pci/pci_delayed_sync.v" |
31 | verilog work "source/pci/pci_wb_slave_unit.v" |
32 | verilog work "source/pci/pci_frame_load_crit.v" |
33 | verilog work "source/pci/pci_mas_ad_en_crit.v" |
34 | verilog work "source/pci/pci_constants.v" |
35 | verilog work "source/pci/pci_wbw_wbr_fifos.v" |
36 | verilog work "source/pci/pci_wb_slave.v" |
37 | verilog work "source/pci/pci_target32_trdy_crit.v" |
38 | verilog work "source/pci/pci_target32_interface.v" |
39 | verilog work "source/pci/pci_wbw_fifo_control.v" |
40 | verilog work "source/pci/pci_wb_tpram.v" |
41 | verilog work "source/pci/pci_par_crit.v" |
42 | verilog work "source/pci/pci_conf_space.v" |
43 | verilog work "source/pci/pci_target32_sm.v" |
44 | verilog work "source/pci/pci_pciw_pcir_fifos.v" |
45 | verilog work "source/pci/pci_serr_en_crit.v" |
46 | verilog work "source/pci/pci_target32_devs_crit.v" |
47 | verilog work "source/pci/pci_out_reg.v" |
48 | verilog work "source/pci/pci_mas_ad_load_crit.v" |
49 | verilog work "source/pci/pci_delayed_write_reg.v" |
50 | verilog work "source/pci/pci_wbs_wbb3_2_wbb2.v" |
51 | verilog work "source/pci/pci_wb_master.v" |
52 | verilog work "source/pci/bus_commands.v" |
53 | verilog work "source/pci/pci_rst_int.v" |
54 | verilog work "source/pci/pci_sync_module.v" |
55 | verilog work "source/pci/pci_master32_sm_if.v" |
56 | verilog work "source/pci/pci_frame_crit.v" |
57 | verilog work "source/pci/pci_user_constants.v" |
58 | verilog work "source/pci/pci_io_mux_ad_load_crit.v" |
59 | verilog work "source/pci/pci_pciw_fifo_control.v" |
60 | verilog work "source/pci/pci_parity_check.v" |
61 | verilog work "source/pci/pci_irdy_out_crit.v" |
62 | verilog work "source/pci/pci_perr_crit.v" |
63 | verilog work "source/pci/pci_mas_ch_state_crit.v" |
64 | verilog work "source/pci/pci_spoci_ctrl.v" |
65 | verilog work "source/pci/pci_wb_addr_mux.v" |
66 | verilog work "source/pci/pci_perr_en_crit.v" |
67 | verilog work "source/pci/pci_target32_clk_en.v" |
68 | verilog work "source/pci/timescale.v" |
69 | verilog work "source/pci/pci_serr_crit.v" |
70 | verilog work "source/pci/pci_frame_en_crit.v" |
71 | verilog work "source/pci/pci_master32_sm.v" |
72 | verilog work "source/pci/pci_pci_tpram.v" |
73 | verilog work "source/pci/pci_cur_out_reg.v" |
74 | verilog work "source/pci/pci_io_mux.v" |
75 | verilog work "source/pci/pci_wbr_fifo_control.v" |
76 | verilog work "source/pci/pci_ram_16x40d.v" |
77 | verilog work "source/pci/pci_io_mux_ad_en_crit.v" |
78 | verilog work "source/pci/pci_async_reset_flop.v" |
79 | verilog work "source/pci/pci_wb_decoder.v" |
80 | verilog work "source/pci/pci_conf_cyc_addr_dec.v" |
81 | verilog work "source/pci/pci_bridge32.v" |
82 | verilog work "source/pci/pci_synchronizer_flop.v" |
83 | verilog work "source/pci/pci_pcir_fifo_control.v" |
84 | verilog work "source/pci/pci_cbe_en_crit.v" |
85 | verilog work "source/pci/pci_pci_decoder.v" |
86 | verilog work "source/pci/pci_in_reg.v" |
87 | vhdl work "source/top.vhd" |
ac5b8271 |
88 | vhdl work "source/phydcm.vhd" |