dcm
[raggedstone] / ethernet / ethernet.prj
CommitLineData
27f6f620 1verilog work "source/ethernet/eth_crc.v"
2verilog work "source/ethernet/eth_cop.v"
3verilog work "source/ethernet/eth_maccontrol.v"
4verilog work "source/ethernet/eth_register.v"
5verilog work "source/ethernet/eth_fifo.v"
6verilog work "source/ethernet/eth_rxstatem.v"
7verilog work "source/ethernet/eth_txcounters.v"
8verilog work "source/ethernet/eth_random.v"
9verilog work "source/ethernet/eth_rxcounters.v"
10verilog work "source/ethernet/eth_top.v"
11verilog work "source/ethernet/eth_shiftreg.v"
12verilog work "source/ethernet/eth_miim.v"
13verilog work "source/ethernet/eth_wishbone.v"
14verilog work "source/ethernet/eth_rxaddrcheck.v"
15verilog work "source/ethernet/xilinx_dist_ram_16x32.v"
16verilog work "source/ethernet/eth_spram_256x32.v"
17verilog work "source/ethernet/eth_txethmac.v"
18verilog work "source/ethernet/timescale.v"
19verilog work "source/ethernet/eth_registers.v"
20verilog work "source/ethernet/eth_defines.v"
21verilog work "source/ethernet/eth_rxethmac.v"
22verilog work "source/ethernet/eth_receivecontrol.v"
23verilog work "source/ethernet/eth_outputcontrol.v"
24verilog work "source/ethernet/eth_txstatem.v"
25verilog work "source/ethernet/eth_transmitcontrol.v"
26verilog work "source/ethernet/eth_macstatus.v"
27verilog work "source/ethernet/eth_clockgen.v"
28verilog work "source/pci/pci_target_unit.v"
29verilog work "source/pci/pci_target32_stop_crit.v"
30verilog work "source/pci/pci_delayed_sync.v"
31verilog work "source/pci/pci_wb_slave_unit.v"
32verilog work "source/pci/pci_frame_load_crit.v"
33verilog work "source/pci/pci_mas_ad_en_crit.v"
34verilog work "source/pci/pci_constants.v"
35verilog work "source/pci/pci_wbw_wbr_fifos.v"
36verilog work "source/pci/pci_wb_slave.v"
37verilog work "source/pci/pci_target32_trdy_crit.v"
38verilog work "source/pci/pci_target32_interface.v"
39verilog work "source/pci/pci_wbw_fifo_control.v"
40verilog work "source/pci/pci_wb_tpram.v"
41verilog work "source/pci/pci_par_crit.v"
42verilog work "source/pci/pci_conf_space.v"
43verilog work "source/pci/pci_target32_sm.v"
44verilog work "source/pci/pci_pciw_pcir_fifos.v"
45verilog work "source/pci/pci_serr_en_crit.v"
46verilog work "source/pci/pci_target32_devs_crit.v"
47verilog work "source/pci/pci_out_reg.v"
48verilog work "source/pci/pci_mas_ad_load_crit.v"
49verilog work "source/pci/pci_delayed_write_reg.v"
50verilog work "source/pci/pci_wbs_wbb3_2_wbb2.v"
51verilog work "source/pci/pci_wb_master.v"
52verilog work "source/pci/bus_commands.v"
53verilog work "source/pci/pci_rst_int.v"
54verilog work "source/pci/pci_sync_module.v"
55verilog work "source/pci/pci_master32_sm_if.v"
56verilog work "source/pci/pci_frame_crit.v"
57verilog work "source/pci/pci_user_constants.v"
58verilog work "source/pci/pci_io_mux_ad_load_crit.v"
59verilog work "source/pci/pci_pciw_fifo_control.v"
60verilog work "source/pci/pci_parity_check.v"
61verilog work "source/pci/pci_irdy_out_crit.v"
62verilog work "source/pci/pci_perr_crit.v"
63verilog work "source/pci/pci_mas_ch_state_crit.v"
64verilog work "source/pci/pci_spoci_ctrl.v"
65verilog work "source/pci/pci_wb_addr_mux.v"
66verilog work "source/pci/pci_perr_en_crit.v"
67verilog work "source/pci/pci_target32_clk_en.v"
68verilog work "source/pci/timescale.v"
69verilog work "source/pci/pci_serr_crit.v"
70verilog work "source/pci/pci_frame_en_crit.v"
71verilog work "source/pci/pci_master32_sm.v"
72verilog work "source/pci/pci_pci_tpram.v"
73verilog work "source/pci/pci_cur_out_reg.v"
74verilog work "source/pci/pci_io_mux.v"
75verilog work "source/pci/pci_wbr_fifo_control.v"
76verilog work "source/pci/pci_ram_16x40d.v"
77verilog work "source/pci/pci_io_mux_ad_en_crit.v"
78verilog work "source/pci/pci_async_reset_flop.v"
79verilog work "source/pci/pci_wb_decoder.v"
80verilog work "source/pci/pci_conf_cyc_addr_dec.v"
81verilog work "source/pci/pci_bridge32.v"
82verilog work "source/pci/pci_synchronizer_flop.v"
83verilog work "source/pci/pci_pcir_fifo_control.v"
84verilog work "source/pci/pci_cbe_en_crit.v"
85verilog work "source/pci/pci_pci_decoder.v"
86verilog work "source/pci/pci_in_reg.v"
87vhdl work "source/top.vhd"
ac5b8271 88vhdl work "source/phydcm.vhd"
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