hack to let the ethernet project build again. timing is broken now...

[raggedstone] / dhwk_old / dhwk.prj

verilog work "source/sync.v"
verilog work "source/pcidec.v"
verilog work "source/pcidmux.v"
verilog work "source/generic_fifo_sc_a.v"
verilog work "source/generic_dpram.v"
verilog work "source/wb_fifo.v"

verilog work "source/pciwbsequ.v"
verilog work "source/pcipargen.v"

vhdl work "source/pciwbsequ.vhd"
vhdl work "source/pfs.vhd"
vhdl work "source/new_pciregs.vhd"
vhdl work "source/pcipargen.vhd"
vhdl work "source/new_pci32tlite.vhd"
vhdl work "source/top_dhwk.vhd"
vhdl work "source/heartbeat.vhd"