fifos

[raggedstone] / heartbeat / source / heartbeat.vhd

library ieee;

use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity heartbeat is
generic (
	divider : std_logic_vector(31 downto 0) := X"01F78A40"
);

port (
	clk_i : in std_logic;
	nrst_i : in std_logic;
	led2_o : out std_logic;
	led3_o : out std_logic;
	led4_o : out std_logic;
	led5_o : out std_logic
);   

end heartbeat;

architecture rtl of heartbeat is
begin

process(clk_i, nrst_i)
variable counter : std_logic_vector(31 downto 0);
variable state : std_logic := '0';
begin

if (clk_i'event AND clk_i = '1') then
	if nrst_i = '0' then
		counter := (others => '0');
        else
		led5_o <= state;
		led2_o <= state;
		led4_o <= not state;
		led3_o <= not state;
		counter := counter + 1;
		if counter = divider then
			state := not state;
			counter := (others => '0');
	        end if;
	end if;
end if;
end process;
end architecture;