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[raggedstone] / dhwk / source / pci / reg_io.vhd

-- VHDL model created from schematic reg_io.sch -- Jan 09 09:34:12 2007

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;


entity REG_IO is
        Port (  AD_REG : In    std_logic_vector (31 downto 0);
                PCI_CLOCK : In    std_logic;
                RESET : In    std_logic;
                WRITE_XX1_0 : In    std_logic;
                WRITE_XX7_6 : In    std_logic;
                REG_OUT_XX0 : Out   std_logic_vector (7 downto 0);
                REG_OUT_XX6 : Out   std_logic_vector (7 downto 0);
                REG_OUT_XX7 : Out   std_logic_vector (7 downto 0) );
end REG_IO;

architecture SCHEMATIC of REG_IO is

        SIGNAL gnd : std_logic := '0';
        SIGNAL vcc : std_logic := '1';


        component REG
                Port (   CLOCK : In    std_logic;
                         REG_IN : In    std_logic_vector (7 downto 0);
                         RESET : In    std_logic;
                         WRITE : In    std_logic;
                         REG_OUT : Out   std_logic_vector (7 downto 0) );
        end component;

begin

        I14 : REG
        Port Map ( CLOCK=>PCI_CLOCK,
        REG_IN(7 downto 0)=>AD_REG(7 downto 0), RESET=>RESET,
        WRITE=>WRITE_XX1_0,
        REG_OUT(7 downto 0)=>REG_OUT_XX0(7 downto 0) );
        I15 : REG
        Port Map ( CLOCK=>PCI_CLOCK,
        REG_IN(7 downto 0)=>AD_REG(31 downto 24), RESET=>RESET,
        WRITE=>WRITE_XX7_6,
        REG_OUT(7 downto 0)=>REG_OUT_XX7(7 downto 0) );
        I16 : REG
        Port Map ( CLOCK=>PCI_CLOCK,
        REG_IN(7 downto 0)=>AD_REG(23 downto 16), RESET=>RESET,
        WRITE=>WRITE_XX7_6,
        REG_OUT(7 downto 0)=>REG_OUT_XX6(7 downto 0) );

end SCHEMATIC;