move address register
[raggedstone] / dhwk / source / CONT_FSM.vhd
CommitLineData
377c0242 1-- J.STELZNER\r
2-- INFORMATIK-3 LABOR\r
3-- 23.08.2006\r
4-- File: CONT_FSM.VHD\r
5\r
6library ieee;\r
7use ieee.std_logic_1164.all ;\r
8\r
9entity CONT_FSM is\r
10 port\r
11 (\r
12 PCI_CLOCK :in std_logic; \r
13 PCI_RSTn :in std_logic; \r
14 IO_READ :in std_logic;\r
15 IO_WRITE :in std_logic;\r
16 CONF_READ :in std_logic;\r
17 CONF_WRITE :in std_logic;\r
18 FIFO_READ :in std_logic;\r
19 READ :out std_logic;--> MUX_SEL(1) , OE_PCI_AD \r
20 PERR_CHECK :out std_logic; \r
21 DEVSELn :out std_logic;\r
22 OE_PCI_PAR :out std_logic;\r
23 OE_PCI_PERR :out std_logic;\r
24 TRDYn :out std_logic;\r
25 PCI_TRDYn :out std_logic; -- s/t/s\r
26 PCI_STOPn :out std_logic; -- s/t/s \r
27 PCI_DEVSELn :out std_logic; -- s/t/s \r
28 FIFO_RDn :out std_logic\r
29 );\r
30end entity CONT_FSM ;\r
31\r
32architecture CONT_FSM_DESIGN of CONT_FSM is\r
33\r
34\r
35\r
36--**********************************************************\r
37--*** CONTROL FSM CODIERUNG ***\r
38--**********************************************************\r
39--\r
40--\r
41--\r
42-- |----------- HELP\r
43-- ||---------- FIFO_READn\r
44-- |||--------- OE_PCI_PERR \r
45-- ||||-------- PERR_CHECK \r
46-- |||||------- TRDYn \r
47-- ||||||------ STOPn \r
48-- |||||||----- DEVSELn \r
49-- ||||||||---- OE_PCI_PAR \r
50-- |||||||||--- OE_CONTROL \r
51-- ||||||||||-- READ / MUX_SEL(1) / OE_PCI_AD \r
52-- |||||||||| \r
53 constant ST_IDLE :std_logic_vector (9 downto 0) := "0100111000" ;-- 138\r
54\r
55 constant ST_READ_1 :std_logic_vector (9 downto 0) := "0100110011" ;-- 133\r
56 constant ST_READ_2 :std_logic_vector (9 downto 0) := "0100000111" ;-- 107\r
57 constant ST_READ_3 :std_logic_vector (9 downto 0) := "0100111111" ;-- 13F\r
58\r
59 constant ST_RD_FIFO_1 :std_logic_vector (9 downto 0) := "0000110011" ;-- 033\r
f822aceb 60 constant ST_RD_FIFO_2 :std_logic_vector (9 downto 0) := "1100110011" ;-- 233\r
377c0242 61\r
62\r
63 constant ST_WRITE_1 :std_logic_vector (9 downto 0) := "0111110010" ;-- 1F2\r
64 constant ST_WRITE_2 :std_logic_vector (9 downto 0) := "0110000010" ;-- 182\r
65 constant ST_WRITE_3 :std_logic_vector (9 downto 0) := "0110111010" ;-- 1BA\r
66\r
67 signal CONTROL_STATE :std_logic_vector (9 downto 0);\r
68\r
69\r
70--signal DEVSELn :std_logic;\r
71 signal STOPn :std_logic;\r
72--signal TRDYn :std_logic;\r
73\r
74--************************************************************\r
75--*** FSM SPEICHER-AUTOMAT ***\r
76--************************************************************\r
77\r
78 attribute syn_state_machine : boolean;\r
79 attribute syn_state_machine of CONTROL_STATE : signal is false;\r
80\r
81begin\r
82\r
83--**********************************************************\r
84--*** CONTROL FSM ***\r
85--**********************************************************\r
86\r
87 process (PCI_CLOCK, PCI_RSTn) \r
88 begin\r
89 if PCI_RSTn = '0' then CONTROL_STATE <= ST_IDLE;\r
90\r
91 elsif (PCI_CLOCK'event and PCI_CLOCK = '1') then\r
92 \r
93 case CONTROL_STATE is\r
94 \r
95 when ST_IDLE => \r
96 if IO_READ = '1' then\r
97 CONTROL_STATE <= ST_READ_1;\r
98\r
99 elsif CONF_READ = '1' then\r
100 CONTROL_STATE <= ST_READ_1; \r
101\r
102 elsif IO_WRITE = '1' then\r
103 CONTROL_STATE <= ST_WRITE_1; \r
104 \r
105 elsif CONF_WRITE = '1' then\r
106 CONTROL_STATE <= ST_WRITE_1;\r
107 \r
108 else CONTROL_STATE <= ST_IDLE;\r
109 end if; \r
110\r
111-- when ST_READ_1 => CONTROL_STATE <= ST_READ_2;\r
112 when ST_READ_1 => \r
113 if FIFO_READ = '1' then\r
114 CONTROL_STATE <= ST_RD_FIFO_1;\r
115 else CONTROL_STATE <= ST_READ_2;\r
116 end if; \r
117\r
118\r
119 when ST_READ_2 => CONTROL_STATE <= ST_READ_3;\r
120 when ST_READ_3 => CONTROL_STATE <= ST_IDLE;\r
121\r
122 when ST_RD_FIFO_1=> CONTROL_STATE <= ST_RD_FIFO_2;\r
123 when ST_RD_FIFO_2=> CONTROL_STATE <= ST_READ_2;\r
124\r
125\r
126 \r
127 when ST_WRITE_1 => CONTROL_STATE <= ST_WRITE_2;\r
128 when ST_WRITE_2 => CONTROL_STATE <= ST_WRITE_3;\r
129 when ST_WRITE_3 => CONTROL_STATE <= ST_IDLE;\r
130\r
131 \r
132 when others => CONTROL_STATE <= ST_IDLE; \r
133\r
134 end case; -- COMM_STATE \r
135 end if; -- CLOCK \r
136 end process; -- PROCESS\r
137\r
138\r
139 READ <= CONTROL_STATE(0);\r
140--OE_CONTROL <= CONTROL_STATE(1);\r
141 OE_PCI_PAR <= CONTROL_STATE(2);\r
142 DEVSELn <= CONTROL_STATE(3);\r
143 STOPn <= CONTROL_STATE(4);\r
144 TRDYn <= CONTROL_STATE(5);\r
145 PERR_CHECK <= CONTROL_STATE(6);\r
146 OE_PCI_PERR <= CONTROL_STATE(7);\r
147\r
148 FIFO_RDn <= CONTROL_STATE(8);\r
149\r
150\r
151 PCI_DEVSELn <= CONTROL_STATE(3) when CONTROL_STATE(1) = '1' else 'Z';\r
152 PCI_STOPn <= STOPn when CONTROL_STATE(1) = '1' else 'Z'; \r
153 PCI_TRDYn <= CONTROL_STATE(5) when CONTROL_STATE(1) = '1' else 'Z'; \r
154\r
155end architecture CONT_FSM_DESIGN ;\r
156\r
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