move address register
[raggedstone] / dhwk / source / Io_mux.vhd
CommitLineData
377c0242 1-- J.STELZNER\r
2-- INFORMATIK-3 LABOR\r
3-- 23.08.2006\r
4-- File: IO_MUX.VHD\r
5\r
6library IEEE;\r
7use IEEE.std_logic_1164.all;\r
8\r
9entity IO_MUX is\r
10 port\r
11 (\r
12 READ_SEL :in std_logic_vector ( 1 downto 0);\r
13 USER_DATA :in std_logic_vector (31 downto 0);\r
14 CONFIG_DATA :in std_logic_vector (31 downto 0);\r
15 PCI_AD :in std_logic_vector (31 downto 0);\r
16 IO_DATA :out std_logic_vector (31 downto 0)\r
17 );\r
18end entity IO_MUX;\r
19\r
20architecture IO_MUX_DESIGN of IO_MUX is\r
21\r
22 signal MUX :std_logic_vector (31 downto 0); \r
23\r
24begin \r
25\r
26 MUX <= PCI_AD when READ_SEL = "00" else -- WRITE_CONFIG \r
27 PCI_AD when READ_SEL = "01" else -- WRITE_IO\r
28 CONFIG_DATA when READ_SEL = "10" else -- READ_CONFIG \r
29 USER_DATA when READ_SEL = "11" else -- READ_IO \r
30 CONFIG_DATA;\r
31\r
32-- MUX;\r
33\r
34 IO_DATA <= MUX;\r
35\r
36end architecture IO_MUX_DESIGN;\r
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