move address register
[raggedstone] / dhwk / source / Io_reg.vhd
CommitLineData
377c0242 1-- J.STELZNER\r
2-- INFORMATIK-3 LABOR\r
3-- 23.08.2006\r
4-- File: IO_MUX.VHD\r
5\r
6library ieee;\r
7use ieee.std_logic_1164.all;\r
8\r
9entity IO_REG is\r
10 port\r
11 (\r
12 PCI_CLOCK :in std_logic;\r
13 PCI_RSTn :in std_logic;\r
14 PCI_FRAMEn :in std_logic;\r
15 PCI_IRDYn :in std_logic;\r
16 PCI_IDSEL :in std_logic;\r
17 PCI_PAR :in std_logic;\r
18 PCI_CBEn :in std_logic_vector ( 3 downto 0);\r
19 OE_PCI_AD :in std_logic;\r
20 IO_DATA :in std_logic_vector (31 downto 0);\r
21 AD_REG :out std_logic_vector (31 downto 0);\r
22 CBE_REGn :out std_logic_vector ( 3 downto 0);\r
23 FRAME_REGn :out std_logic; \r
24 IRDY_REGn :out std_logic; \r
25 IDSEL_REG :out std_logic;\r
26 PAR_REG :out std_logic; \r
27 PCI_AD :out std_logic_vector (31 downto 0) -- t/s\r
28 );\r
29end entity IO_REG;\r
30\r
31architecture IO_REG_DESIGN of IO_REG is\r
32\r
33 signal REG_AD :std_logic_vector (31 downto 0); \r
34 signal REG_CBEn :std_logic_vector ( 3 downto 0);\r
35 signal REG_FRAMEn :std_logic;\r
36 signal REG_IRDYn :std_logic;\r
37 signal REG_IDSEL :std_logic;\r
38 signal REG_PAR :std_logic;\r
39\r
40begin \r
41\r
42 process (PCI_CLOCK, PCI_RSTn) \r
43 begin\r
44 if PCI_RSTn = '0' then\r
45\r
46 REG_AD <= X"00000000";\r
47 REG_CBEn <= "0000";\r
48 REG_FRAMEn <= '1';\r
49 REG_IRDYn <= '1';\r
50 REG_IDSEL <= '0';\r
51 REG_PAR <= '0';\r
52\r
53 elsif (PCI_CLOCK'event and PCI_CLOCK = '1') then\r
54\r
55 REG_AD <= IO_DATA;\r
56 REG_CBEn <= PCI_CBEn;\r
57 REG_FRAMEn <= PCI_FRAMEn;\r
58 REG_IRDYn <= PCI_IRDYn;\r
59 REG_IDSEL <= PCI_IDSEL;\r
60 REG_PAR <= PCI_PAR;\r
61\r
62 end if;\r
63 end process;\r
64\r
65 PCI_AD <= REG_AD when OE_PCI_AD ='1' else (others => 'Z');\r
66\r
67 AD_REG <= REG_AD;\r
68 CBE_REGn <= REG_CBEn;\r
69 FRAME_REGn <= REG_FRAMEn;\r
70 IRDY_REGn <= REG_IRDYn;\r
71 IDSEL_REG <= REG_IDSEL;\r
72 PAR_REG <= REG_PAR;\r
73\r
74end architecture IO_REG_DESIGN;\r
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