move address register
[raggedstone] / dhwk / source / config_rd_0.vhd
CommitLineData
377c0242 1-- J.STELZNER\r
2-- INFORMATIK-3 LABOR\r
3-- 23.08.2006\r
4-- File: CONFIG_RD_0.VHD\r
5\r
6library IEEE;\r
7use IEEE.std_logic_1164.all;\r
8\r
9entity CONFIG_RD_0 is\r
10 port\r
11 (\r
12 ADDR_REG :in std_logic_vector (31 downto 0);\r
13 CF_RD_COM :in std_logic;\r
14 READ_SEL :out std_logic_vector ( 2 downto 0)\r
15 );\r
16end entity CONFIG_RD_0;\r
17\r
18architecture CONFIG_RD_0_DESIGN of CONFIG_RD_0 is\r
19\r
20--\r
21--\r
22--\r
23--\r
24--\r
25-- PCI Configuration Space Header\r
26--\r
27-- \ Bit\r
28-- \\r
29--Address |31 24|23 16|15 8|7 0| \r
30-----------------------------------------------------------------\r
31--00 |Device ID |Vendor ID | \r
32--04 |Status |Command |\r
33--08 |Class Code |Revision ID|\r
34--0C |BIST |Header Type|Latency T. |Cache L.S. |\r
35--10-24 |Base Address Register |\r
36--28 |Cardbus CIS Pointer |\r
37--2C |Subsystem ID |Subsystem Vendor ID |\r
38--30 |Expansion ROM Base Address |\r
39--34 |Reserved |\r
40--38 |Reserved |\r
41--3C |Max_Lat |Min_Gnt |Int_Pin |Int_Line |\r
42--40-FF | |\r
43-----------------------------------------------------------------\r
44\r
45\r
46--PCI Bus Commands \r
47--C/BE[3..0] Command Type\r
48--------------------------------------\r
49-- 0000 Interrupt Acknowledge\r
50-- 0001 Special Cycle\r
51-- 0010 I/O Read\r
52-- 0011 I/O Write\r
53-- 0100 Reserved\r
54-- 0101 Reserved\r
55-- 0110 Memory Read\r
56-- 0111 Memory Write\r
57--\r
58-- 1000 Reserved\r
59-- 1001 Reserved\r
60-- 1010 Configuration Read\r
61-- 1011 Configuration Write\r
62-- 1100 Memory Read Multiple \r
63-- 1101 Dual Address Cycle\r
64-- 1110 Memory Read Line\r
65-- 1111 Memory Write and Invalidate\r
66\r
67\r
68--PCI Byte Enable \r
69--C/BE[3..0] gueltige Datenbits \r
70-------------------------------\r
71-- 0000 AD 31..0\r
72-- 1000 AD 23..0\r
73-- 1100 AD 15..0\r
74-- 1110 AD 7..0\r
75\r
76 constant CMD_INT_ACK :std_logic_vector(3 downto 0) := "0000";\r
77 constant CMD_SP_CYC :std_logic_vector(3 downto 0) := "0001";\r
78 constant CMD_IO_READ :std_logic_vector(3 downto 0) := "0010";\r
79 constant CMD_IO_WRITE :std_logic_vector(3 downto 0) := "0011";\r
80 constant CMD_RES_4 :std_logic_vector(3 downto 0) := "0100";\r
81 constant CMD_RES_5 :std_logic_vector(3 downto 0) := "0101";\r
82 constant CMD_MEM_READ :std_logic_vector(3 downto 0) := "0110";\r
83 constant CMD_MEM_WRITE :std_logic_vector(3 downto 0) := "0111";\r
84 constant CMD_RES_8 :std_logic_vector(3 downto 0) := "1000";\r
85 constant CMD_RES_9 :std_logic_vector(3 downto 0) := "1001";\r
86 constant CMD_CONF_READ :std_logic_vector(3 downto 0) := "1010";\r
87 constant CMD_CONF_WRITE :std_logic_vector(3 downto 0) := "1011";\r
88 constant CMD_MEM_READ_M :std_logic_vector(3 downto 0) := "1100";\r
89 constant CMD_DU_ADR_CYC :std_logic_vector(3 downto 0) := "1101";\r
90 constant CMD_MEN_READ_L :std_logic_vector(3 downto 0) := "1110";\r
91 constant CMD_MEM_WRITE_I :std_logic_vector(3 downto 0) := "1111";\r
92\r
93 signal MUX :std_logic_vector(31 downto 0); \r
94 signal CONFIG_ADDR :std_logic_vector( 7 downto 0); \r
95\r
96begin\r
97\r
98 CONFIG_ADDR(7 downto 0) <= ADDR_REG(7 downto 0);\r
99\r
100--*******************************************************************\r
101--*********************** PCI Read Address **************************\r
102--*******************************************************************\r
103\r
104 process (CF_RD_COM, CONFIG_ADDR) \r
105 begin\r
106\r
107 if CF_RD_COM = '1' then\r
108\r
109 if CONFIG_ADDR = X"00" then READ_SEL <= "000";\r
110 elsif CONFIG_ADDR = X"04" then READ_SEL <= "001";\r
111 elsif CONFIG_ADDR = X"08" then READ_SEL <= "010";\r
112 elsif CONFIG_ADDR = X"10" then READ_SEL <= "011";\r
113 elsif CONFIG_ADDR = X"3C" then READ_SEL <= "100";\r
114 elsif CONFIG_ADDR = X"40" then READ_SEL <= "101";\r
115 else READ_SEL <= "111";\r
116 end if;\r
117 else READ_SEL <= "111";\r
118 end if;\r
119 end process;\r
120\r
121end architecture CONFIG_RD_0_DESIGN;\r
122\r
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