move address register
[raggedstone] / dhwk / source / config_space_header.vhd
CommitLineData
377c0242 1-- VHDL model created from schematic config_space_header.sch -- Jan 09 09:34:16 2007\r
2\r
3\r
4\r
5LIBRARY ieee;\r
6\r
7USE ieee.std_logic_1164.ALL;\r
8USE ieee.numeric_std.ALL;\r
9\r
10\r
11entity CONFIG_SPACE_HEADER is\r
12 Port ( AD_REG : In std_logic_vector (31 downto 0);\r
13 ADDR_REG : In std_logic_vector (31 downto 0);\r
14 CBE_REGn : In std_logic_vector (3 downto 0);\r
15 CF_RD_COM : In std_logic;\r
16 CF_WR_COM : In std_logic;\r
17 IRDY_REGn : In std_logic;\r
18 PCI_CLOCK : In std_logic;\r
19 PCI_RSTn : In std_logic;\r
20 PERR : In std_logic;\r
21 REVISION_ID : In std_logic_vector (7 downto 0);\r
22 SERR : In std_logic;\r
23 TRDYn : In std_logic;\r
24 VENDOR_ID : In std_logic_vector (15 downto 0);\r
25 CONF_DATA : Out std_logic_vector (31 downto 0);\r
26 CONF_DATA_04H : Out std_logic_vector (31 downto 0);\r
27 CONF_DATA_10H : Out std_logic_vector (31 downto 0) );\r
28end CONFIG_SPACE_HEADER;\r
29\r
30architecture SCHEMATIC of CONFIG_SPACE_HEADER is\r
31\r
32 SIGNAL gnd : std_logic := '0';\r
33 SIGNAL vcc : std_logic := '1';\r
34\r
35 signal CONF_WR_04H : std_logic;\r
36 signal CONF_WR_10H : std_logic;\r
37 signal CONF_WR_3CH : std_logic;\r
38 signal CONF_READ_SEL : std_logic_vector (2 downto 0);\r
39 signal CONF_DATA_10H_DUMMY : std_logic_vector (31 downto 0);\r
40 signal CONF_DATA_04H_DUMMY : std_logic_vector (31 downto 0);\r
41 signal CONF_DATA_3CH : std_logic_vector (31 downto 0);\r
42 signal CONF_DATA_08H : std_logic_vector (31 downto 0);\r
43 signal CONF_DATA_00H : std_logic_vector (31 downto 0);\r
44\r
45 component CONFIG_MUX_0\r
46 Port ( CONF_DATA_00H : In std_logic_vector (31 downto 0);\r
47 CONF_DATA_04H : In std_logic_vector (31 downto 0);\r
48 CONF_DATA_08H : In std_logic_vector (31 downto 0);\r
49 CONF_DATA_10H : In std_logic_vector (31 downto 0);\r
50 CONF_DATA_3CH : In std_logic_vector (31 downto 0);\r
51 READ_SEL : In std_logic_vector (2 downto 0);\r
52 CONF_DATA : Out std_logic_vector (31 downto 0) );\r
53 end component;\r
54\r
55 component CONFIG_RD_0\r
56 Port ( ADDR_REG : In std_logic_vector (31 downto 0);\r
57 CF_RD_COM : In std_logic;\r
58 READ_SEL : Out std_logic_vector (2 downto 0) );\r
59 end component;\r
60\r
61 component CONFIG_WR_0\r
62 Port ( ADDR_REG : In std_logic_vector (31 downto 0);\r
63 CF_WR_COM : In std_logic;\r
64 IRDY_REGn : In std_logic;\r
65 TRDYn : In std_logic;\r
66 CONF_WR_04H : Out std_logic;\r
67 CONF_WR_10H : Out std_logic;\r
68 CONF_WR_3CH : Out std_logic );\r
69 end component;\r
70\r
71 component CONFIG_3CH\r
72 Port ( AD_REG : In std_logic_vector (31 downto 0);\r
73 CBE_REGn : In std_logic_vector (3 downto 0);\r
74 CONF_WR_3CH : In std_logic;\r
75 PCI_CLOCK : In std_logic;\r
76 PCI_RSTn : In std_logic;\r
77 CONF_DATA_3CH : Out std_logic_vector (31 downto 0) );\r
78 end component;\r
79\r
80 component CONFIG_10H\r
81 Port ( AD_REG : In std_logic_vector (31 downto 0);\r
82 CBE_REGn : In std_logic_vector (3 downto 0);\r
83 CONF_WR_10H : In std_logic;\r
84 PCI_CLOCK : In std_logic;\r
85 PCI_RSTn : In std_logic;\r
86 CONF_DATA_10H : Out std_logic_vector (31 downto 0) );\r
87 end component;\r
88\r
89 component CONFIG_08H\r
90 Port ( REVISION_ID : In std_logic_vector (7 downto 0);\r
91 CONF_DATA_08H : Out std_logic_vector (31 downto 0) );\r
92 end component;\r
93\r
94 component CONFIG_00H\r
95 Port ( VENDOR_ID : In std_logic_vector (15 downto 0);\r
96 CONF_DATA_00H : Out std_logic_vector (31 downto 0) );\r
97 end component;\r
98\r
99 component CONFIG_04H\r
100 Port ( AD_REG : In std_logic_vector (31 downto 0);\r
101 CBE_REGn : In std_logic_vector (3 downto 0);\r
102 CONF_WR_04H : In std_logic;\r
103 PCI_CLOCK : In std_logic;\r
104 PCI_RSTn : In std_logic;\r
105 PERR : In std_logic;\r
106 SERR : In std_logic;\r
107 CONF_DATA_04H : Out std_logic_vector (31 downto 0) );\r
108 end component;\r
109\r
110begin\r
111\r
112 CONF_DATA_04H <= CONF_DATA_04H_DUMMY;\r
113 CONF_DATA_10H <= CONF_DATA_10H_DUMMY;\r
114\r
115 I10 : CONFIG_MUX_0\r
116 Port Map ( CONF_DATA_00H(31 downto 0)=>CONF_DATA_00H(31 downto 0),\r
117 CONF_DATA_04H(31 downto 0)=>CONF_DATA_04H_DUMMY(31 downto 0),\r
118 CONF_DATA_08H(31 downto 0)=>CONF_DATA_08H(31 downto 0),\r
119 CONF_DATA_10H(31 downto 0)=>CONF_DATA_10H_DUMMY(31 downto 0),\r
120 CONF_DATA_3CH(31 downto 0)=>CONF_DATA_3CH(31 downto 0),\r
121 READ_SEL(2 downto 0)=>CONF_READ_SEL(2 downto 0),\r
122 CONF_DATA(31 downto 0)=>CONF_DATA(31 downto 0) );\r
123 I9 : CONFIG_RD_0\r
124 Port Map ( ADDR_REG(31 downto 0)=>ADDR_REG(31 downto 0),\r
125 CF_RD_COM=>CF_RD_COM,\r
126 READ_SEL(2 downto 0)=>CONF_READ_SEL(2 downto 0) );\r
127 I8 : CONFIG_WR_0\r
128 Port Map ( ADDR_REG(31 downto 0)=>ADDR_REG(31 downto 0),\r
129 CF_WR_COM=>CF_WR_COM, IRDY_REGn=>IRDY_REGn,\r
130 TRDYn=>TRDYn, CONF_WR_04H=>CONF_WR_04H,\r
131 CONF_WR_10H=>CONF_WR_10H, CONF_WR_3CH=>CONF_WR_3CH );\r
132 I6 : CONFIG_3CH\r
133 Port Map ( AD_REG(31 downto 0)=>AD_REG(31 downto 0),\r
134 CBE_REGn(3 downto 0)=>CBE_REGn(3 downto 0),\r
135 CONF_WR_3CH=>CONF_WR_3CH, PCI_CLOCK=>PCI_CLOCK,\r
136 PCI_RSTn=>PCI_RSTn,\r
137 CONF_DATA_3CH(31 downto 0)=>CONF_DATA_3CH(31 downto 0) );\r
138 I5 : CONFIG_10H\r
139 Port Map ( AD_REG(31 downto 0)=>AD_REG(31 downto 0),\r
140 CBE_REGn(3 downto 0)=>CBE_REGn(3 downto 0),\r
141 CONF_WR_10H=>CONF_WR_10H, PCI_CLOCK=>PCI_CLOCK,\r
142 PCI_RSTn=>PCI_RSTn,\r
143 CONF_DATA_10H(31 downto 0)=>CONF_DATA_10H_DUMMY(31 downto 0) );\r
144 I4 : CONFIG_08H\r
145 Port Map ( REVISION_ID(7 downto 0)=>REVISION_ID(7 downto 0),\r
146 CONF_DATA_08H(31 downto 0)=>CONF_DATA_08H(31 downto 0) );\r
147 I3 : CONFIG_00H\r
148 Port Map ( VENDOR_ID(15 downto 0)=>VENDOR_ID(15 downto 0),\r
149 CONF_DATA_00H(31 downto 0)=>CONF_DATA_00H(31 downto 0) );\r
150 I2 : CONFIG_04H\r
151 Port Map ( AD_REG(31 downto 0)=>AD_REG(31 downto 0),\r
152 CBE_REGn(3 downto 0)=>CBE_REGn(3 downto 0),\r
153 CONF_WR_04H=>CONF_WR_04H, PCI_CLOCK=>PCI_CLOCK,\r
154 PCI_RSTn=>PCI_RSTn, PERR=>PERR, SERR=>SERR,\r
155 CONF_DATA_04H(31 downto 0)=>CONF_DATA_04H_DUMMY(31 downto 0) );\r
156\r
157end SCHEMATIC;\r
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