move address register
[raggedstone] / dhwk / source / connecting_fsm.vhd
CommitLineData
377c0242 1-- J.STELZNER\r
2-- INFORMATIK-3 LABOR\r
3-- 23.08.2006\r
4-- File: CONNECTING_FSM.VHD\r
5\r
6library ieee ;\r
7use ieee.std_logic_1164.all ;\r
8\r
9entity CONNECTING_FSM is\r
10 port\r
11 (\r
12 PCI_CLOCK :in std_logic; \r
13 RESET :in std_logic; \r
14 PSC_ENABLE :in std_logic;\r
15 SYNC_S_FIFO_EFn :in std_logic;\r
16 SPC_ENABLE :in std_logic;\r
17 SYNC_R_FIFO_FFn :in std_logic;\r
18 S_FIFO_Q_OUT :in std_logic_vector(7 downto 0);\r
19 S_FIFO_READn :out std_logic;\r
20 R_FIFO_WRITEn :out std_logic;\r
21 R_FIFO_D_IN :out std_logic_vector(7 downto 0) \r
22 );\r
23end entity CONNECTING_FSM;\r
24\r
25architecture CONNECTING_FSM_DESIGN of CONNECTING_FSM is\r
26\r
27 signal REG :std_logic_vector(7 downto 0);\r
28 signal HELP_0,HELP_1 :std_logic;\r
29 signal SIG_LOAD :std_logic;\r
30\r
31\r
32--**********************************************************\r
33--*** CONNECTING FSM CODIERUNG ***\r
34--**********************************************************\r
35--\r
36--\r
37-- ---------- HELP_0\r
38-- |--------- HELP_1 \r
39-- ||-------- LOAD \r
40-- |||------- WRITE \r
41-- ||||------ READ \r
42-- ||||| \r
43 constant S0 :std_logic_vector(4 downto 0) := "00011";--\r
44 constant S1 :std_logic_vector(4 downto 0) := "01010";--READ\r
45 constant S2 :std_logic_vector(4 downto 0) := "10010";--READ\r
46 constant S3 :std_logic_vector(4 downto 0) := "11110";--READ,LOAD\r
47 constant S4 :std_logic_vector(4 downto 0) := "11011";--\r
48 constant S5 :std_logic_vector(4 downto 0) := "01001";--WRITE\r
49 constant S6 :std_logic_vector(4 downto 0) := "10001";--WRITE\r
50 constant S7 :std_logic_vector(4 downto 0) := "11001";--WRITE\r
51\r
52 signal STATES :std_logic_vector(4 downto 0);\r
53\r
54--************************************************************\r
55--*** FSM SPEICHER-AUTOMAT ***\r
56--************************************************************\r
57\r
58 attribute syn_state_machine : boolean;\r
59 attribute syn_state_machine of STATES : signal is false;\r
60\r
61--************************************************************\r
62--*** REGISTER BESCHREIBUNG ***\r
63--************************************************************\r
64\r
65begin\r
66\r
67 process (PCI_CLOCK) \r
68 begin\r
69 if (PCI_CLOCK'event and PCI_CLOCK = '1') then\r
70 if SIG_LOAD = '1' then REG <= S_FIFO_Q_OUT;\r
71 elsif SIG_LOAD = '0' then REG <= REG; \r
72 end if;\r
73 end if;\r
74 end process;\r
75\r
76--************************************************************\r
77--*** FSM BESCHREIBUNG ***\r
78--************************************************************\r
79\r
80 process (PCI_CLOCK)\r
81 begin \r
82 if (PCI_CLOCK'event and PCI_CLOCK = '1') then\r
83 \r
84 if RESET = '1' then STATES <= S0;\r
85 else\r
86 \r
87 case STATES is\r
88\r
89 when S0 => \r
90 if PSC_ENABLE = '1' and\r
91 SPC_ENABLE = '1' and\r
92 SYNC_S_FIFO_EFn = '1' then\r
93\r
94 STATES <= S1;\r
95 else \r
96 STATES <= S0;\r
97 end if;\r
98\r
99 when S1 => STATES <= S2;\r
100 when S2 => STATES <= S3;\r
101 when S3 => STATES <= S4;\r
102\r
103 when S4 => \r
104 if SYNC_R_FIFO_FFn = '1' then\r
105\r
106 STATES <= S5;\r
107 else \r
108 STATES <= S4;\r
109 end if;\r
110\r
111 when S5 => STATES <= S6;\r
112 when S6 => STATES <= S7;\r
113 when S7 => STATES <= S0;\r
114\r
115 when others => \r
116\r
117 STATES <= S0; \r
118\r
119 end case; -- STATES \r
120 end if; -- RESET \r
121 end if; -- PCI_CLOCK \r
122 end process; -- PROCESS\r
123\r
124--************************************************************\r
125--*** ZUWEISUNG signal/out <= STATES ***\r
126--************************************************************\r
127\r
128 HELP_0 <= STATES(4); \r
129 HELP_1 <= STATES(3);\r
130 SIG_LOAD <= STATES(2);\r
131 R_FIFO_WRITEn <= STATES(1);\r
132 S_FIFO_READn <= STATES(0);\r
133\r
134 R_FIFO_D_IN <= REG;\r
135\r
136end architecture CONNECTING_FSM_DESIGN;\r
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