move address register
[raggedstone] / dhwk / source / fifo_io_control.vhd
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377c0242 1-- $Id: fifo_io_control.vhd,v 1.1 2007-03-10 11:24:03 sithglan Exp $\r
2\r
3library IEEE;\r
4use IEEE.std_logic_1164.all;\r
5\r
6entity FIFO_IO_CONTROL is\r
7 port\r
8 (\r
9 PCI_CLOCK :in std_logic;\r
10 WRITE_XX1_0 :in std_logic; -- PCI Write\r
11 FIFO_RDn :in std_logic; -- FIFO Read (low active)\r
12 RESET :in std_logic;\r
13 SYNC_FLAG_1 :in std_logic; -- Recv FIFO Empty (low active)\r
14 SYNC_FLAG_7 :in std_logic; -- Send FIFO Full (low active)\r
15 S_FIFO_RESETn :out std_logic; -- Send FIFO Reset (low active)\r
16 R_FIFO_RESETn :out std_logic; -- Recv FIFO Reset (low active)\r
17 S_FIFO_WRITEn :out std_logic; -- Send FIFO Write (low active)\r
18 R_FIFO_READn :out std_logic; -- Recv FIFO Read (low active)\r
19 S_FIFO_RETRANSMITn :out std_logic; -- Send FIFO Retransmit (low active)\r
20 R_FIFO_RETRANSMITn :out std_logic; -- Recv FIFO Retransmit (low active)\r
21 S_ERROR :out std_logic; -- Send ERROR\r
22 R_ERROR :out std_logic; -- Recv ERROR\r
23 SR_ERROR :out std_logic -- Send / Recv Error\r
24 ); \r
25end entity FIFO_IO_CONTROL;\r
26\r
27architecture FIFO_IO_CONTROL_DESIGN of FIFO_IO_CONTROL is\r
28\r
29signal SIG_S_ERROR :std_logic; -- Send Error\r
30signal SIG_R_ERROR :std_logic; -- Recv Error\r
31\r
32begin\r
33\r
34-- FIFO Write\r
35\r
36 process (PCI_CLOCK) \r
37 begin \r
38 if (PCI_CLOCK'event and PCI_CLOCK = '1') then \r
39 if (RESET = '1') then\r
40 S_FIFO_WRITEn <= '1';\r
41 SIG_S_ERROR <= '0';\r
42\r
43 elsif (WRITE_XX1_0 = '0') then\r
44 S_FIFO_WRITEn <= '1';\r
45\r
46 elsif (WRITE_XX1_0 = '1') then\r
47 if (SYNC_FLAG_7 = '0') then\r
48 SIG_S_ERROR <= '1';\r
49\r
50 elsif (SYNC_FLAG_7 = '1') then\r
51 S_FIFO_WRITEn <= '0';\r
52 SIG_S_ERROR <= '0';\r
53 end if;\r
54 end if;\r
55 end if;\r
56 end process; \r
57\r
58 S_ERROR <= SIG_S_ERROR;\r
59 \r
60-- FIFO Read\r
61\r
62 R_FIFO_READn <= FIFO_RDn; \r
63\r
64-- Receive Error\r
65\r
66process (PCI_CLOCK) \r
67begin \r
68 if (PCI_CLOCK'event and PCI_CLOCK ='1') then \r
69 if (RESET = '1') then\r
70 SIG_R_ERROR <= '0';\r
71\r
72 elsif (FIFO_RDn = '0' and SYNC_FLAG_1 = '0') then\r
73 SIG_R_ERROR <= '1';\r
74 end if;\r
75 end if;\r
76end process; \r
77\r
78 R_ERROR <= SIG_R_ERROR; \r
79\r
80-- Send or Receive Error\r
81\r
82process (PCI_CLOCK) \r
83begin \r
84 if (PCI_CLOCK'event and PCI_CLOCK ='1') then \r
85 SR_ERROR <= SIG_S_ERROR or SIG_R_ERROR;\r
86 end if;\r
87end process; \r
88\r
89-- FIFO Reset\r
90\r
91process (PCI_CLOCK) \r
92begin \r
93 if (PCI_CLOCK'event and PCI_CLOCK ='1') then \r
94 S_FIFO_RESETn <= not RESET; \r
95 R_FIFO_RESETn <= not RESET; \r
96 end if;\r
97end process; \r
98\r
99\r
100-- FIFO Retransmit\r
101\r
102process (PCI_CLOCK) \r
103begin \r
104 if (PCI_CLOCK'event and PCI_CLOCK ='1') then \r
105 S_FIFO_RETRANSMITn <= '1'; \r
106 R_FIFO_RETRANSMITn <= '1'; \r
107 end if;\r
108end process; \r
109 \r
110end architecture FIFO_IO_CONTROL_DESIGN;\r
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