move address register
[raggedstone] / dhwk / source / io_mux_reg.vhd
CommitLineData
377c0242 1-- VHDL model created from schematic io_mux_reg.sch -- Jan 09 09:34:13 2007\r
2\r
3\r
4\r
5LIBRARY ieee;\r
6\r
7USE ieee.std_logic_1164.ALL;\r
8USE ieee.numeric_std.ALL;\r
9\r
10\r
11entity IO_MUX_REG is\r
12 Port ( CONFIG_DATA : In std_logic_vector (31 downto 0);\r
13 LOAD_ADDR_REG : In std_logic;\r
14 PCI_CBEn : In std_logic_vector (3 downto 0);\r
15 PCI_CLOCK : In std_logic;\r
16 PCI_FRAMEn : In std_logic;\r
17 PCI_IDSEL : In std_logic;\r
18 PCI_IRDYn : In std_logic;\r
19 PCI_PAR : In std_logic;\r
20 PCI_RSTn : In std_logic;\r
21 READ_SEL : In std_logic_vector (1 downto 0);\r
22 USER_DATA : In std_logic_vector (31 downto 0);\r
23 PCI_AD : InOut std_logic_vector (31 downto 0);\r
24 AD_REG : Out std_logic_vector (31 downto 0);\r
25 ADDR_REG : Out std_logic_vector (31 downto 0);\r
26 CBE_REGn : Out std_logic_vector (3 downto 0);\r
27 FRAME_REGn : Out std_logic;\r
28 IDSEL_REG : Out std_logic;\r
29 IRDY_REGn : Out std_logic;\r
30 PAR_REG : Out std_logic );\r
31end IO_MUX_REG;\r
32\r
33architecture SCHEMATIC of IO_MUX_REG is\r
34\r
35 SIGNAL gnd : std_logic := '0';\r
36 SIGNAL vcc : std_logic := '1';\r
37\r
38 signal IO_DATA : std_logic_vector (31 downto 0);\r
39 signal AD_REG_DUMMY : std_logic_vector (31 downto 0);\r
40\r
d452afd5 41 component ADDRESS_REGISTER\r
377c0242 42 Port ( AD_REG : In std_logic_vector (31 downto 0);\r
43 LOAD_ADDR_REG : In std_logic;\r
44 PCI_CLOCK : In std_logic;\r
45 PCI_RSTn : In std_logic;\r
46 ADDR_REG : Out std_logic_vector (31 downto 0) );\r
47 end component;\r
48\r
49 component IO_REG\r
50 Port ( IO_DATA : In std_logic_vector (31 downto 0);\r
51 OE_PCI_AD : In std_logic;\r
52 PCI_CBEn : In std_logic_vector (3 downto 0);\r
53 PCI_CLOCK : In std_logic;\r
54 PCI_FRAMEn : In std_logic;\r
55 PCI_IDSEL : In std_logic;\r
56 PCI_IRDYn : In std_logic;\r
57 PCI_PAR : In std_logic;\r
58 PCI_RSTn : In std_logic;\r
59 AD_REG : Out std_logic_vector (31 downto 0);\r
60 CBE_REGn : Out std_logic_vector (3 downto 0);\r
61 FRAME_REGn : Out std_logic;\r
62 IDSEL_REG : Out std_logic;\r
63 IRDY_REGn : Out std_logic;\r
64 PAR_REG : Out std_logic;\r
65 PCI_AD : Out std_logic_vector (31 downto 0) );\r
66 end component;\r
67\r
68 component IO_MUX\r
69 Port ( CONFIG_DATA : In std_logic_vector (31 downto 0);\r
70 PCI_AD : In std_logic_vector (31 downto 0);\r
71 READ_SEL : In std_logic_vector (1 downto 0);\r
72 USER_DATA : In std_logic_vector (31 downto 0);\r
73 IO_DATA : Out std_logic_vector (31 downto 0) );\r
74 end component;\r
75\r
76begin\r
77\r
78 AD_REG <= AD_REG_DUMMY;\r
79\r
d452afd5 80 I5 : ADDRESS_REGISTER\r
377c0242 81 Port Map ( AD_REG(31 downto 0)=>AD_REG_DUMMY(31 downto 0),\r
82 LOAD_ADDR_REG=>LOAD_ADDR_REG, PCI_CLOCK=>PCI_CLOCK,\r
83 PCI_RSTn=>PCI_RSTn,\r
84 ADDR_REG(31 downto 0)=>ADDR_REG(31 downto 0) );\r
85 I1 : IO_REG\r
86 Port Map ( IO_DATA(31 downto 0)=>IO_DATA(31 downto 0),\r
87 OE_PCI_AD=>READ_SEL(1),\r
88 PCI_CBEn(3 downto 0)=>PCI_CBEn(3 downto 0),\r
89 PCI_CLOCK=>PCI_CLOCK, PCI_FRAMEn=>PCI_FRAMEn,\r
90 PCI_IDSEL=>PCI_IDSEL, PCI_IRDYn=>PCI_IRDYn,\r
91 PCI_PAR=>PCI_PAR, PCI_RSTn=>PCI_RSTn,\r
92 AD_REG(31 downto 0)=>AD_REG_DUMMY(31 downto 0),\r
93 CBE_REGn(3 downto 0)=>CBE_REGn(3 downto 0),\r
94 FRAME_REGn=>FRAME_REGn, IDSEL_REG=>IDSEL_REG,\r
95 IRDY_REGn=>IRDY_REGn, PAR_REG=>PAR_REG,\r
96 PCI_AD(31 downto 0)=>PCI_AD(31 downto 0) );\r
97 I2 : IO_MUX\r
98 Port Map ( CONFIG_DATA(31 downto 0)=>CONFIG_DATA(31 downto 0),\r
99 PCI_AD(31 downto 0)=>PCI_AD(31 downto 0),\r
100 READ_SEL(1 downto 0)=>READ_SEL(1 downto 0),\r
101 USER_DATA(31 downto 0)=>USER_DATA(31 downto 0),\r
102 IO_DATA(31 downto 0)=>IO_DATA(31 downto 0) );\r
103\r
104end SCHEMATIC;\r
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