696ded12 |
1 | ----------------------------------------------------------------------------- |
2612d712 |
2 | -- -- |
3 | -- Copyright (c) 1997 by Synplicity, Inc. All rights reserved. -- |
4 | -- -- |
5 | -- This source file may be used and distributed without restriction -- |
6 | -- provided that this copyright statement is not removed from the file -- |
7 | -- and that any derivative work contains this copyright notice. -- |
8 | -- -- |
9 | -- Primitive library for post synthesis simulation -- |
10 | -- These models are not intended for efficient synthesis -- |
11 | -- -- |
696ded12 |
12 | ----------------------------------------------------------------------------- |
13 | library ieee; |
14 | use ieee.std_logic_1164.all; |
15 | entity prim_counter is |
2612d712 |
16 | generic (w : integer := 8); |
17 | port ( |
18 | q : buffer std_logic_vector(w - 1 downto 0); |
19 | cout : out std_logic; |
20 | d : in std_logic_vector(w - 1 downto 0); |
21 | cin : in std_logic; |
22 | clk : in std_logic; |
23 | rst : in std_logic; |
24 | load : in std_logic; |
25 | en : in std_logic; |
26 | updn : in std_logic |
27 | ); |
696ded12 |
28 | end prim_counter; |
29 | |
30 | architecture beh of prim_counter is |
2612d712 |
31 | signal nextq : std_logic_vector(w - 1 downto 0); |
696ded12 |
32 | begin |
2612d712 |
33 | nxt: process (q, cin, updn) |
34 | variable i : integer; |
35 | variable nextc, c : std_logic; |
36 | begin |
37 | nextc := cin; |
38 | for i in 0 to w - 1 loop |
39 | c := nextc; |
40 | nextq(i) <= c xor (not updn) xor q(i); |
41 | nextc := (c and (not updn)) or |
42 | (c and q(i)) or |
43 | ((not updn) and q(i)); |
44 | end loop; |
45 | cout <= nextc; |
46 | end process; |
47 | |
48 | ff : process (clk, rst) |
49 | begin |
50 | if rst = '1' then |
51 | q <= (others => '0'); |
52 | elsif rising_edge(clk) then |
53 | q <= nextq; |
54 | end if; |
55 | end process ff; |
696ded12 |
56 | end beh; |
57 | |
58 | library ieee; |
59 | use ieee.std_logic_1164.all; |
60 | entity prim_dff is |
2612d712 |
61 | port (q : out std_logic; |
62 | d : in std_logic; |
63 | clk : in std_logic; |
64 | r : in std_logic := '0'; |
65 | s : in std_logic := '0'); |
696ded12 |
66 | end prim_dff; |
67 | |
68 | architecture beh of prim_dff is |
69 | begin |
2612d712 |
70 | ff : process (clk, r, s) |
71 | begin |
72 | if r = '1' then |
73 | q <= '0'; |
74 | elsif s = '1' then |
75 | q <= '1'; |
76 | elsif rising_edge(clk) then |
77 | q <= d; |
78 | end if; |
79 | end process ff; |
696ded12 |
80 | end beh; |
81 | |
82 | library ieee; |
83 | use ieee.std_logic_1164.all; |
84 | entity prim_latch is |
2612d712 |
85 | port (q : out std_logic; |
86 | d : in std_logic; |
87 | clk : in std_logic; |
88 | r : in std_logic := '0'; |
89 | s : in std_logic := '0'); |
696ded12 |
90 | end prim_latch; |
91 | |
92 | architecture beh of prim_latch is |
93 | begin |
2612d712 |
94 | q <= '0' when r = '1' else |
95 | '1' when s = '1' else |
96 | d when clk = '1'; |
696ded12 |
97 | end beh; |
98 | |
99 | |
100 | library ieee; |
101 | use ieee.std_logic_1164.all; |
102 | use ieee.std_logic_unsigned.all; |
103 | |
104 | entity prim_ramd is |
2612d712 |
105 | generic ( |
106 | data_width : integer := 4; |
107 | addr_width : integer := 5); |
108 | port ( |
109 | dout : out std_logic_vector(data_width-1 downto 0); |
110 | aout : in std_logic_vector(addr_width-1 downto 0); |
111 | din : in std_logic_vector(data_width-1 downto 0); |
112 | ain : in std_logic_vector(addr_width-1 downto 0); |
113 | we : in std_logic; |
114 | clk : in std_logic); |
696ded12 |
115 | end prim_ramd; |
116 | |
117 | architecture beh of prim_ramd is |
118 | |
2612d712 |
119 | constant depth : integer := 2** addr_width; |
120 | type mem_type is array (depth-1 downto 0) of std_logic_vector (data_width-1 downto 0); |
121 | signal mem: mem_type; |
696ded12 |
122 | |
2612d712 |
123 | begin |
696ded12 |
124 | |
2612d712 |
125 | dout <= mem(conv_integer(aout)); |
696ded12 |
126 | |
2612d712 |
127 | process (clk) |
128 | begin |
129 | if rising_edge(clk) then |
130 | if (we = '1') then |
131 | mem(conv_integer(ain)) <= din; |
132 | end if; |
133 | end if; |
134 | end process; |
696ded12 |
135 | |
2612d712 |
136 | end beh; |
696ded12 |
137 | |
138 | |
139 | library ieee; |
140 | use ieee.std_logic_1164.all; |
141 | package components is |
2612d712 |
142 | component prim_counter |
143 | generic (w : integer); |
144 | port ( |
145 | q : buffer std_logic_vector(w - 1 downto 0); |
146 | cout : out std_logic; |
147 | d : in std_logic_vector(w - 1 downto 0); |
148 | cin : in std_logic; |
149 | clk : in std_logic; |
150 | rst : in std_logic; |
151 | load : in std_logic; |
152 | en : in std_logic; |
153 | updn : in std_logic |
154 | ); |
155 | end component; |
156 | component prim_dff |
157 | port (q : out std_logic; |
158 | d : in std_logic; |
159 | clk : in std_logic; |
160 | r : in std_logic := '0'; |
161 | s : in std_logic := '0'); |
162 | end component; |
163 | component prim_latch |
164 | port (q : out std_logic; |
165 | d : in std_logic; |
166 | clk : in std_logic; |
167 | r : in std_logic := '0'; |
168 | s : in std_logic := '0'); |
169 | end component; |
170 | |
171 | component prim_ramd is |
172 | generic ( |
173 | data_width : integer := 4; |
174 | addr_width : integer := 5); |
175 | port ( |
176 | dout : out std_logic_vector(data_width-1 downto 0); |
177 | aout : in std_logic_vector(addr_width-1 downto 0); |
178 | din : in std_logic_vector(data_width-1 downto 0); |
179 | ain : in std_logic_vector(addr_width-1 downto 0); |
180 | we : in std_logic; |
181 | clk : in std_logic); |
182 | end component; |
696ded12 |
183 | |
184 | end components; |