lot of new files
[raggedstone] / ethernet / ethernet.prj
CommitLineData
e00b64cc 1vhdl work "source/top.vhd"
2verilog work "source/ethernet/eth_crc.v"
3verilog work "source/ethernet/eth_cop.v"
4verilog work "source/ethernet/eth_maccontrol.v"
5verilog work "source/ethernet/eth_register.v"
6verilog work "source/ethernet/eth_fifo.v"
7verilog work "source/ethernet/eth_rxstatem.v"
8verilog work "source/ethernet/eth_txcounters.v"
9verilog work "source/ethernet/eth_random.v"
10verilog work "source/ethernet/eth_rxcounters.v"
11verilog work "source/ethernet/eth_top.v"
12verilog work "source/ethernet/eth_shiftreg.v"
13verilog work "source/ethernet/eth_miim.v"
14verilog work "source/ethernet/eth_wishbone.v"
15verilog work "source/ethernet/eth_rxaddrcheck.v"
16verilog work "source/ethernet/xilinx_dist_ram_16x32.v"
17verilog work "source/ethernet/eth_spram_256x32.v"
18verilog work "source/ethernet/eth_txethmac.v"
19verilog work "source/ethernet/timescale.v"
20verilog work "source/ethernet/eth_registers.v"
21verilog work "source/ethernet/eth_defines.v"
22verilog work "source/ethernet/eth_rxethmac.v"
23verilog work "source/ethernet/eth_receivecontrol.v"
24verilog work "source/ethernet/eth_outputcontrol.v"
25verilog work "source/ethernet/eth_txstatem.v"
26verilog work "source/ethernet/eth_transmitcontrol.v"
27verilog work "source/ethernet/eth_macstatus.v"
28verilog work "source/ethernet/eth_clockgen.v"
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