+= use xilinx block ram for ethernet

[raggedstone] / dhwk_old / source / vga_main.vhd

---------------------------------------------------------------------\r
-- vga_main.vhd  Demo VGA configuration module.\r
---------------------------------------------------------------------\r
-- 	Author: Barron Barnett\r
--            Copyright 2004 Digilent, Inc.\r
---------------------------------------------------------------------\r
--\r
-- This project is compatible with Xilinx ISE or Xilinx WebPack tools.\r
--\r
-- Inputs: \r
--		mclk  - System Clock\r
-- Outputs:\r
--		hs		- Horizontal Sync\r
--		vs		- Vertical Sync\r
--		red	- Red Output\r
--		grn	- Green Output\r
--		blu	- Blue Output\r
--\r
-- This module creates a three line pattern on a vga display using a\r
-- a vertical refresh rate of 60Hz.  This is done by dividing the\r
-- system clock in half and using that for the pixel clock.  This in\r
-- turn drives the vertical sync when the horizontal sync has reached\r
-- its reset point.  All data displayed is done by basic value\r
-- comparisons.\r
------------------------------------------------------------------------\r
-- Revision History:\r
--	 07/01/2004(BarronB): created\r
------------------------------------------------------------------------\r
library IEEE;\r
use IEEE.STD_LOGIC_1164.ALL;\r
use IEEE.STD_LOGIC_ARITH.ALL;\r
use IEEE.STD_LOGIC_UNSIGNED.ALL;\r
\r
\r
entity vgaController is\r
    Port ( mclk : in std_logic;\r
           hs : out std_logic;\r
           vs : out std_logic;\r
           red : out std_logic;\r
           grn : out std_logic;\r
           blu : out std_logic);\r
end vgaController;\r
\r
architecture Behavioral of vgaController is\r
\r
\r
	constant hpixels		: std_logic_vector(9 downto 0) := "1100100000";	 --Value of pixels in a horizontal line\r
	constant vlines		: std_logic_vector(9 downto 0) := "1000001001";	 --Number of horizontal lines in the display\r
	\r
	constant hbp			: std_logic_vector(9 downto 0) := "0010010000";	 --Horizontal back porch\r
	constant hfp			: std_logic_vector(9 downto 0) := "1100010000";	 --Horizontal front porch\r
	constant	vbp			: std_logic_vector(9 downto 0) := "0000011111";	 --Vertical back porch\r
	constant vfp			: std_logic_vector(9	downto 0) := "0111111111";	 --Vertical front porch\r
	\r
	signal hc, vc			: std_logic_vector(9 downto 0);						 --These are the Horizontal and Vertical counters\r
	signal clkdiv			: std_logic;												 --Clock divider\r
	signal vidon			: std_logic;												 --Tells whether or not its ok to display data\r
	signal vsenable		: std_logic;												 --Enable for the Vertical counter\r
\r
begin\r
	--This cuts the 50Mhz clock in half\r
	process(mclk)\r
		begin\r
			if(mclk = '1' and mclk'EVENT) then\r
				clkdiv <= not clkdiv;\r
			end if;\r
		end process;																			\r
\r
	--Runs the horizontal counter\r
	process(clkdiv)\r
		begin\r
			if(clkdiv = '1' and clkdiv'EVENT) then\r
				if hc = hpixels then														 --If the counter has reached the end of pixel count\r
					hc <= "0000000000";													 --reset the counter\r
					vsenable <= '1';														 --Enable the vertical counter to increment\r
				else\r
					hc <= hc + 1;															 --Increment the horizontal counter\r
					vsenable <= '0';														 --Leave the vsenable off\r
				end if;\r
		end if;\r
	end process;\r
\r
	hs <= '1' when hc(9 downto 7) = "000" else '0';								 --Horizontal Sync Pulse\r
\r
	process(clkdiv)\r
	begin\r
		if(clkdiv = '1' and clkdiv'EVENT and vsenable = '1') then			 --Increment when enabled\r
			if vc = vlines then															 --Reset when the number of lines is reached\r
				vc <= "0000000000";\r
			else vc <= vc + 1;															 --Increment the vertical counter\r
			end if;\r
		end if;\r
	end process;\r
\r
	vs <= '1' when vc(9 downto 1) = "000000000" else '0';						 --Vertical Sync Pulse\r
\r
  	red <= '1' when (hc = "1010101100" and vidon ='1') else '0';			 --Red pixel on at a specific horizontal count\r
  	grn <= '1' when (hc = "0100000100" and vidon ='1') else '0';			 --Green pixel on at a specific horizontal count\r
  	blu <= '1' when (vc = "0100100001" and vidon ='1') else '0';			 --Blue pixel on at a specific vertical count\r
\r
	vidon <= '1' when (((hc < hfp) and (hc > hbp)) or ((vc < vfp) and (vc > vbp))) else '0';	--Enable video out when within the porches\r
\r
end Behavioral;\r