+= use xilinx block ram for ethernet
[raggedstone] / ethernet / source / ethernet / eth_defines.v
CommitLineData
40a1f26c 1//////////////////////////////////////////////////////////////////////
2//// ////
3//// eth_defines.v ////
4//// ////
5//// This file is part of the Ethernet IP core project ////
6//// http://www.opencores.org/projects/ethmac/ ////
7//// ////
8//// Author(s): ////
9//// - Igor Mohor (igorM@opencores.org) ////
10//// ////
11//// All additional information is available in the Readme.txt ////
12//// file. ////
13//// ////
14//////////////////////////////////////////////////////////////////////
15//// ////
16//// Copyright (C) 2001, 2002 Authors ////
17//// ////
18//// This source file may be used and distributed without ////
19//// restriction provided that this copyright statement is not ////
20//// removed from the file and that any derivative work contains ////
21//// the original copyright notice and the associated disclaimer. ////
22//// ////
23//// This source file is free software; you can redistribute it ////
24//// and/or modify it under the terms of the GNU Lesser General ////
25//// Public License as published by the Free Software Foundation; ////
26//// either version 2.1 of the License, or (at your option) any ////
27//// later version. ////
28//// ////
29//// This source is distributed in the hope that it will be ////
30//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
31//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
32//// PURPOSE. See the GNU Lesser General Public License for more ////
33//// details. ////
34//// ////
35//// You should have received a copy of the GNU Lesser General ////
36//// Public License along with this source; if not, download it ////
37//// from http://www.opencores.org/lgpl.shtml ////
38//// ////
39//////////////////////////////////////////////////////////////////////
40//
41// CVS Revision History
42//
43// $Log: eth_defines.v,v $
e252c592 44// Revision 1.2 2007-03-20 22:17:38 sithglan
45// += use xilinx block ram for ethernet
46//
47// Revision 1.1 2007/03/19 16:44:04 sithglan
48// lot of new files
40a1f26c 49//
50// Revision 1.34 2005/02/21 12:48:06 igorm
51// Warning fixes.
52//
53// Revision 1.33 2003/11/12 18:24:58 tadejm
54// WISHBONE slave changed and tested from only 32-bit accesss to byte access.
55//
56// Revision 1.32 2003/10/17 07:46:13 markom
57// mbist signals updated according to newest convention
58//
59// Revision 1.31 2003/08/14 16:42:58 simons
60// Artisan ram instance added.
61//
62// Revision 1.30 2003/06/13 11:55:37 mohor
63// Define file in eth_cop.v is changed to eth_defines.v. Some defines were
64// moved from tb_eth_defines.v to eth_defines.v.
65//
66// Revision 1.29 2002/11/19 18:13:49 mohor
67// r_MiiMRst is not used for resetting the MIIM module. wb_rst used instead.
68//
69// Revision 1.28 2002/11/15 14:27:15 mohor
70// Since r_Rst bit is not used any more, default value is changed to 0xa000.
71//
72// Revision 1.27 2002/11/01 18:19:34 mohor
73// Defines fixed to use generic RAM by default.
74//
75// Revision 1.26 2002/10/24 18:53:03 mohor
76// fpga define added.
77//
78// Revision 1.3 2002/10/11 16:57:54 igorm
79// eth_defines.v tagged with rel_5 used.
80//
81// Revision 1.25 2002/10/10 16:47:44 mohor
82// Defines changed to have ETH_ prolog.
83// ETH_WISHBONE_B# define added.
84//
85// Revision 1.24 2002/10/10 16:33:11 mohor
86// Bist added.
87//
88// Revision 1.23 2002/09/23 18:22:48 mohor
89// Virtual Silicon RAM might be used in the ASIC implementation of the ethernet
90// core.
91//
92// Revision 1.22 2002/09/04 18:36:49 mohor
93// Defines for control registers added (ETH_TXCTRL and ETH_RXCTRL).
94//
95// Revision 1.21 2002/08/16 22:09:47 mohor
96// Defines for register width added. mii_rst signal in MIIMODER register
97// changed.
98//
99// Revision 1.20 2002/08/14 19:31:48 mohor
100// Register TX_BD_NUM is changed so it contains value of the Tx buffer descriptors. No
101// need to multiply or devide any more.
102//
103// Revision 1.19 2002/07/23 15:28:31 mohor
104// Ram , used for BDs changed from generic_spram to eth_spram_256x32.
105//
106// Revision 1.18 2002/05/03 10:15:50 mohor
107// Outputs registered. Reset changed for eth_wishbone module.
108//
109// Revision 1.17 2002/04/24 08:52:19 mohor
110// Compiler directives added. Tx and Rx fifo size incremented. A "late collision"
111// bug fixed.
112//
113// Revision 1.16 2002/03/19 12:53:29 mohor
114// Some defines that are used in testbench only were moved to tb_eth_defines.v
115// file.
116//
117// Revision 1.15 2002/02/26 16:11:32 mohor
118// Number of interrupts changed
119//
120// Revision 1.14 2002/02/16 14:03:44 mohor
121// Registered trimmed. Unused registers removed.
122//
123// Revision 1.13 2002/02/16 13:06:33 mohor
124// EXTERNAL_DMA used instead of WISHBONE_DMA.
125//
126// Revision 1.12 2002/02/15 10:58:31 mohor
127// Changed that were lost with last update put back to the file.
128//
129// Revision 1.11 2002/02/14 20:19:41 billditt
130// Modified for Address Checking,
131// addition of eth_addrcheck.v
132//
133// Revision 1.10 2002/02/12 17:01:19 mohor
134// HASH0 and HASH1 registers added.
135
136// Revision 1.9 2002/02/08 16:21:54 mohor
137// Rx status is written back to the BD.
138//
139// Revision 1.8 2002/02/05 16:44:38 mohor
140// Both rx and tx part are finished. Tested with wb_clk_i between 10 and 200
141// MHz. Statuses, overrun, control frame transmission and reception still need
142// to be fixed.
143//
144// Revision 1.7 2002/01/23 10:28:16 mohor
145// Link in the header changed.
146//
147// Revision 1.6 2001/12/05 15:00:16 mohor
148// RX_BD_NUM changed to TX_BD_NUM (holds number of TX descriptors
149// instead of the number of RX descriptors).
150//
151// Revision 1.5 2001/12/05 10:21:37 mohor
152// ETH_RX_BD_ADR register deleted. ETH_RX_BD_NUM is used instead.
153//
154// Revision 1.4 2001/11/13 14:23:56 mohor
155// Generic memory model is used. Defines are changed for the same reason.
156//
157// Revision 1.3 2001/10/18 12:07:11 mohor
158// Status signals changed, Adress decoding changed, interrupt controller
159// added.
160//
161// Revision 1.2 2001/09/24 15:02:56 mohor
162// Defines changed (All precede with ETH_). Small changes because some
163// tools generate warnings when two operands are together. Synchronization
164// between two clocks domains in eth_wishbonedma.v is changed (due to ASIC
165// demands).
166//
167// Revision 1.1 2001/08/06 14:44:29 mohor
168// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
169// Include files fixed to contain no path.
170// File names and module names changed ta have a eth_ prologue in the name.
171// File eth_timescale.v is used to define timescale
172// All pin names on the top module are changed to contain _I, _O or _OE at the end.
173// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
174// and Mdo_OE. The bidirectional signal must be created on the top level. This
175// is done due to the ASIC tools.
176//
177// Revision 1.1 2001/07/30 21:23:42 mohor
178// Directory structure changed. Files checked and joind together.
179//
180//
181//
182//
183//
184
185
186
187//`define ETH_BIST // Bist for usage with Virtual Silicon RAMS
188
189`define ETH_MBIST_CTRL_WIDTH 3 // width of MBIST control bus
190
191// Ethernet implemented in Xilinx Chips (uncomment following lines)
e252c592 192`define ETH_FIFO_XILINX // Use Xilinx distributed ram for tx and rx fifo
40a1f26c 193// `define ETH_XILINX_RAMB4 // Selection of the used memory for Buffer descriptors
194 // Core is going to be implemented in Virtex FPGA and contains Virtex
195 // specific elements.
196
197// Ethernet implemented in Altera Chips (uncomment following lines)
198//`define ETH_ALTERA_ALTSYNCRAM
199
200// Ethernet implemented in ASIC with Virtual Silicon RAMs
201// `define ETH_VIRTUAL_SILICON_RAM // Virtual Silicon RAMS used storing buffer decriptors (ASIC implementation)
202
203// Ethernet implemented in ASIC with Artisan RAMs
204// `define ETH_ARTISAN_RAM // Artisan RAMS used storing buffer decriptors (ASIC implementation)
205
206// Uncomment when Avalon bus is used
207//`define ETH_AVALON_BUS
208
209`define ETH_MODER_ADR 8'h0 // 0x0
210`define ETH_INT_SOURCE_ADR 8'h1 // 0x4
211`define ETH_INT_MASK_ADR 8'h2 // 0x8
212`define ETH_IPGT_ADR 8'h3 // 0xC
213`define ETH_IPGR1_ADR 8'h4 // 0x10
214`define ETH_IPGR2_ADR 8'h5 // 0x14
215`define ETH_PACKETLEN_ADR 8'h6 // 0x18
216`define ETH_COLLCONF_ADR 8'h7 // 0x1C
217`define ETH_TX_BD_NUM_ADR 8'h8 // 0x20
218`define ETH_CTRLMODER_ADR 8'h9 // 0x24
219`define ETH_MIIMODER_ADR 8'hA // 0x28
220`define ETH_MIICOMMAND_ADR 8'hB // 0x2C
221`define ETH_MIIADDRESS_ADR 8'hC // 0x30
222`define ETH_MIITX_DATA_ADR 8'hD // 0x34
223`define ETH_MIIRX_DATA_ADR 8'hE // 0x38
224`define ETH_MIISTATUS_ADR 8'hF // 0x3C
225`define ETH_MAC_ADDR0_ADR 8'h10 // 0x40
226`define ETH_MAC_ADDR1_ADR 8'h11 // 0x44
227`define ETH_HASH0_ADR 8'h12 // 0x48
228`define ETH_HASH1_ADR 8'h13 // 0x4C
229`define ETH_TX_CTRL_ADR 8'h14 // 0x50
230`define ETH_RX_CTRL_ADR 8'h15 // 0x54
231
232
233`define ETH_MODER_DEF_0 8'h00
234`define ETH_MODER_DEF_1 8'hA0
235`define ETH_MODER_DEF_2 1'h0
236`define ETH_INT_MASK_DEF_0 7'h0
237`define ETH_IPGT_DEF_0 7'h12
238`define ETH_IPGR1_DEF_0 7'h0C
239`define ETH_IPGR2_DEF_0 7'h12
240`define ETH_PACKETLEN_DEF_0 8'h00
241`define ETH_PACKETLEN_DEF_1 8'h06
242`define ETH_PACKETLEN_DEF_2 8'h40
243`define ETH_PACKETLEN_DEF_3 8'h00
244`define ETH_COLLCONF_DEF_0 6'h3f
245`define ETH_COLLCONF_DEF_2 4'hF
246`define ETH_TX_BD_NUM_DEF_0 8'h40
247`define ETH_CTRLMODER_DEF_0 3'h0
248`define ETH_MIIMODER_DEF_0 8'h64
249`define ETH_MIIMODER_DEF_1 1'h0
250`define ETH_MIIADDRESS_DEF_0 5'h00
251`define ETH_MIIADDRESS_DEF_1 5'h00
252`define ETH_MIITX_DATA_DEF_0 8'h00
253`define ETH_MIITX_DATA_DEF_1 8'h00
254`define ETH_MIIRX_DATA_DEF 16'h0000 // not written from WB
255`define ETH_MAC_ADDR0_DEF_0 8'h00
256`define ETH_MAC_ADDR0_DEF_1 8'h00
257`define ETH_MAC_ADDR0_DEF_2 8'h00
258`define ETH_MAC_ADDR0_DEF_3 8'h00
259`define ETH_MAC_ADDR1_DEF_0 8'h00
260`define ETH_MAC_ADDR1_DEF_1 8'h00
261`define ETH_HASH0_DEF_0 8'h00
262`define ETH_HASH0_DEF_1 8'h00
263`define ETH_HASH0_DEF_2 8'h00
264`define ETH_HASH0_DEF_3 8'h00
265`define ETH_HASH1_DEF_0 8'h00
266`define ETH_HASH1_DEF_1 8'h00
267`define ETH_HASH1_DEF_2 8'h00
268`define ETH_HASH1_DEF_3 8'h00
269`define ETH_TX_CTRL_DEF_0 8'h00 //
270`define ETH_TX_CTRL_DEF_1 8'h00 //
271`define ETH_TX_CTRL_DEF_2 1'h0 //
272`define ETH_RX_CTRL_DEF_0 8'h00
273`define ETH_RX_CTRL_DEF_1 8'h00
274
275
276`define ETH_MODER_WIDTH_0 8
277`define ETH_MODER_WIDTH_1 8
278`define ETH_MODER_WIDTH_2 1
279`define ETH_INT_SOURCE_WIDTH_0 7
280`define ETH_INT_MASK_WIDTH_0 7
281`define ETH_IPGT_WIDTH_0 7
282`define ETH_IPGR1_WIDTH_0 7
283`define ETH_IPGR2_WIDTH_0 7
284`define ETH_PACKETLEN_WIDTH_0 8
285`define ETH_PACKETLEN_WIDTH_1 8
286`define ETH_PACKETLEN_WIDTH_2 8
287`define ETH_PACKETLEN_WIDTH_3 8
288`define ETH_COLLCONF_WIDTH_0 6
289`define ETH_COLLCONF_WIDTH_2 4
290`define ETH_TX_BD_NUM_WIDTH_0 8
291`define ETH_CTRLMODER_WIDTH_0 3
292`define ETH_MIIMODER_WIDTH_0 8
293`define ETH_MIIMODER_WIDTH_1 1
294`define ETH_MIICOMMAND_WIDTH_0 3
295`define ETH_MIIADDRESS_WIDTH_0 5
296`define ETH_MIIADDRESS_WIDTH_1 5
297`define ETH_MIITX_DATA_WIDTH_0 8
298`define ETH_MIITX_DATA_WIDTH_1 8
299`define ETH_MIIRX_DATA_WIDTH 16 // not written from WB
300`define ETH_MIISTATUS_WIDTH 3 // not written from WB
301`define ETH_MAC_ADDR0_WIDTH_0 8
302`define ETH_MAC_ADDR0_WIDTH_1 8
303`define ETH_MAC_ADDR0_WIDTH_2 8
304`define ETH_MAC_ADDR0_WIDTH_3 8
305`define ETH_MAC_ADDR1_WIDTH_0 8
306`define ETH_MAC_ADDR1_WIDTH_1 8
307`define ETH_HASH0_WIDTH_0 8
308`define ETH_HASH0_WIDTH_1 8
309`define ETH_HASH0_WIDTH_2 8
310`define ETH_HASH0_WIDTH_3 8
311`define ETH_HASH1_WIDTH_0 8
312`define ETH_HASH1_WIDTH_1 8
313`define ETH_HASH1_WIDTH_2 8
314`define ETH_HASH1_WIDTH_3 8
315`define ETH_TX_CTRL_WIDTH_0 8
316`define ETH_TX_CTRL_WIDTH_1 8
317`define ETH_TX_CTRL_WIDTH_2 1
318`define ETH_RX_CTRL_WIDTH_0 8
319`define ETH_RX_CTRL_WIDTH_1 8
320
321
322// Outputs are registered (uncomment when needed)
323`define ETH_REGISTERED_OUTPUTS
324
325// Settings for TX FIFO
326`define ETH_TX_FIFO_CNT_WIDTH 5
327`define ETH_TX_FIFO_DEPTH 16
328`define ETH_TX_FIFO_DATA_WIDTH 32
329
330// Settings for RX FIFO
331`define ETH_RX_FIFO_CNT_WIDTH 5
332`define ETH_RX_FIFO_DEPTH 16
333`define ETH_RX_FIFO_DATA_WIDTH 32
334
335// Burst length
336`define ETH_BURST_LENGTH 4 // Change also ETH_BURST_CNT_WIDTH
337`define ETH_BURST_CNT_WIDTH 3 // The counter must be width enough to count to ETH_BURST_LENGTH
338
339// WISHBONE interface is Revision B3 compliant (uncomment when needed)
340//`define ETH_WISHBONE_B3
341
342
343// Following defines are needed when eth_cop.v is used. Otherwise they may be deleted.
344`define ETH_BASE 32'hd0000000
345`define ETH_WIDTH 32'h800
346`define MEMORY_BASE 32'h2000
347`define MEMORY_WIDTH 32'h10000
348
349`define M1_ADDRESSED_S1 ( (m1_wb_adr_i >= `ETH_BASE) & (m1_wb_adr_i < (`ETH_BASE + `ETH_WIDTH )) )
350`define M1_ADDRESSED_S2 ( (m1_wb_adr_i >= `MEMORY_BASE) & (m1_wb_adr_i < (`MEMORY_BASE + `MEMORY_WIDTH)) )
351`define M2_ADDRESSED_S1 ( (m2_wb_adr_i >= `ETH_BASE) & (m2_wb_adr_i < (`ETH_BASE + `ETH_WIDTH )) )
352`define M2_ADDRESSED_S2 ( (m2_wb_adr_i >= `MEMORY_BASE) & (m2_wb_adr_i < (`MEMORY_BASE + `MEMORY_WIDTH)) )
353// Previous defines are only needed for eth_cop.v
354
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