perl -p -i -e "s/PCI_CLOCK'event and PCI_CLOCK = '1'/rising_edge(PCI_CLOCK)/" *.vhd
[raggedstone] / dhwk / source / pci / parity_out.vhd
CommitLineData
696ded12 1-- J.STELZNER
2-- INFORMATIK-3 LABOR
3-- 23.08.2006
4-- File: PARITY_OUT.VHD
5
6library ieee;
7use ieee.std_logic_1164.all;
8
9entity PARITY_OUT is
2612d712 10 port(
11 PCI_CLOCK :in std_logic;
12 PCI_RSTn :in std_logic;
13 PAR_IN :in std_logic_vector ( 2 downto 0);
14 PAR_REG :in std_logic;
15 SERR_CHECK :in std_logic;
16 PERR_CHECK :in std_logic;
17 OE_PCI_PAR :in std_logic;
18 OE_PCI_PERR :in std_logic;
19 PA_ER_RE :in std_logic;
20 SERR_ENA :in std_logic;
21 PCI_PAR_IN :in std_logic;
22 PERR :out std_logic;
23 SERR :out std_logic;
24 PCI_PERRn :out std_logic; -- s/t/s
25 PCI_SERRn :out std_logic; -- o/d
26 PCI_PAR :out std_logic -- t/s
27 );
28end entity PARITY_OUT;
696ded12 29
30architecture PARITY_OUT_DESIGN of PARITY_OUT is
31
2612d712 32 signal PAR :std_logic;
33 signal PAR_FF :std_logic;
34 signal SERR_FF :std_logic;
35 signal PERR_FF :std_logic;
696ded12 36
2612d712 37begin
696ded12 38
2612d712 39 PAR <= ( PAR_IN(2) xor PAR_IN(1) xor PAR_IN(0) );
696ded12 40
2612d712 41 process (PCI_CLOCK, PCI_RSTn)
42 begin
43 if PCI_RSTn = '0' then PAR_FF <= '0';
44 PERR_FF <= '0';
45 SERR_FF <= '0';
696ded12 46
e687cadb 47 elsif (rising_edge(PCI_CLOCK)) then
2612d712 48 SERR_FF <= ((PCI_PAR_IN xor PAR) and SERR_CHECK) and PA_ER_RE and SERR_ENA and (not SERR_FF);
49 PERR_FF <= ((PCI_PAR_IN xor PAR) and PERR_CHECK) and (not PERR_FF);
50 end if;
51end process;
696ded12 52
2612d712 53SERR <= SERR_FF;
54PERR <= PERR_FF;
696ded12 55
2612d712 56PCI_PAR <= PAR_FF when OE_PCI_PAR = '1' else 'Z';
57PCI_SERRn <= '0' when SERR_FF = '1' else 'Z';
58PCI_PERRn <= not PERR_FF when OE_PCI_PERR = '1' and PA_ER_RE = '1' else 'Z';
696ded12 59
60end architecture PARITY_OUT_DESIGN;
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