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[raggedstone] / heartbeat / source / heartbeat.vhd
CommitLineData
152884e6 1library ieee;
2
3use ieee.std_logic_1164.all;
4use ieee.std_logic_unsigned.all;
5
6entity heartbeat is
7generic (
e7843394 8 divider : std_logic_vector(31 downto 0) := "00000000001111101111000101001000"
152884e6 9);
10
11port (
12 clk_i : in std_logic;
13 nrst_i : in std_logic;
f7be0147 14 led2_o : out std_logic;
15 led3_o : out std_logic;
16 led4_o : out std_logic;
17 led5_o : out std_logic
152884e6 18);
19
20end heartbeat;
21
22architecture rtl of heartbeat is
23begin
24
25process(clk_i, nrst_i)
26variable counter : std_logic_vector(31 downto 0);
e7843394 27variable state : std_logic_vector(3 downto 0) := "0001";
28variable direction : std_logic := '0';
152884e6 29begin
30
31if (clk_i'event AND clk_i = '1') then
32 if nrst_i = '0' then
33 counter := (others => '0');
34 else
e7843394 35 led2_o <= state(0);
36 led3_o <= state(1);
37 led4_o <= state(2);
38 led5_o <= state(3);
152884e6 39 counter := counter + 1;
40 if counter = divider then
e7843394 41 if state(3) = '1' then
42 direction := '1';
43 end if;
44
45 if state(0) = '1' then
46 direction := '0';
47 end if;
48
49 if direction = '0' then
50 state(3 downto 1) := state(2 downto 0);
51 state(0) := '0';
52 else
53 state(2 downto 0) := state(3 downto 1);
54 state(3) := '0';
55 end if;
82cc0f36 56 counter := (others => '0');
152884e6 57 end if;
58 end if;
59end if;
60end process;
61end architecture;
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