dhwk
[raggedstone] / dhwk_old / source / sync.v
CommitLineData
ebba63a9 1module sync2 (clk, d, q);
2 input clk;
3 input d;
4 output q;
5 reg q;
6
7 always @(posedge clk)
8 begin
9 q <= d;
10 end
11endmodule
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