+= userland
[raggedstone] / heartbeat / source / top_raggedstone.vhd
CommitLineData
95764a11 1--+-------------------------------------------------------------------------------------------------+\r
2--| |\r
3--| File: top.vhd |\r
4--| |\r
5--| Components: pci32lite.vhd |\r
6--| pciwbsequ.vhd |\r
7--| pcidmux.vhd |\r
8--| pciregs.vhd |\r
9--| pcipargen.vhd |\r
10--| -- Libs -- |\r
11--| ona.vhd |\r
12--| |\r
13--| Description: RS1 PCI Demo : (TOP) Main file. |\r
14--| |\r
15--| |\r
16--| |\r
17--+-------------------------------------------------------------------------------------------------+\r
18--| |\r
19--| Revision history : |\r
20--| Date Version Author Description |\r
21--| |\r
22--| |\r
23--| To do: |\r
24--| |\r
25--+-------------------------------------------------------------------------------------------------+\r
26\r
27\r
28--+-----------------------------------------------------------------------------+\r
29--| LIBRARIES |\r
30--+-----------------------------------------------------------------------------+\r
31\r
32library ieee;\r
33use ieee.std_logic_1164.all;\r
34use ieee.std_logic_arith.all;\r
35use ieee.std_logic_unsigned.all;\r
36\r
37--+-----------------------------------------------------------------------------+\r
38--| ENTITY |\r
39--+-----------------------------------------------------------------------------+\r
40\r
ad16d1e3 41entity raggedstone is\r
95764a11 42port (\r
43\r
44 -- General \r
45 PCI_CLK : in std_logic;\r
46 PCI_nRES : in std_logic;\r
47 \r
48 -- PCI target 32bits\r
49 PCI_AD : inout std_logic_vector(31 downto 0);\r
50 PCI_CBE : in std_logic_vector(3 downto 0);\r
51 PCI_PAR : out std_logic; \r
52 PCI_nFRAME : in std_logic;\r
53 PCI_nIRDY : in std_logic;\r
54 PCI_nTRDY : out std_logic;\r
55 PCI_nDEVSEL : out std_logic;\r
56 PCI_nSTOP : out std_logic;\r
57 PCI_IDSEL : in std_logic;\r
58 PCI_nPERR : out std_logic;\r
59 PCI_nSERR : out std_logic;\r
60 PCI_nINT : out std_logic;\r
61 \r
95764a11 62 -- debug signals\r
f7be0147 63 LED3 : out std_logic;\r
64 LED2 : out std_logic;\r
65 LED4 : out std_logic;\r
36a53ce2 66 LED5 : out std_logic;\r
67 IDE1 : out std_logic;\r
68 IDE2 : out std_logic;\r
69 IDE3 : out std_logic;\r
70 IDE4 : out std_logic\r
95764a11 71\r
72);\r
ad16d1e3 73end raggedstone;\r
95764a11 74\r
75\r
76--+-----------------------------------------------------------------------------+\r
77--| ARCHITECTURE |\r
78--+-----------------------------------------------------------------------------+\r
79\r
ad16d1e3 80architecture raggedstone_arch of raggedstone is\r
95764a11 81\r
82\r
83--+-----------------------------------------------------------------------------+\r
84--| COMPONENTS |\r
85--+-----------------------------------------------------------------------------+\r
86\r
87component pci32tlite\r
88port (\r
89\r
90 -- General \r
91 clk33 : in std_logic;\r
92 nrst : in std_logic;\r
93 \r
94 -- PCI target 32bits\r
95 ad : inout std_logic_vector(31 downto 0);\r
96 cbe : in std_logic_vector(3 downto 0);\r
97 par : out std_logic; \r
98 frame : in std_logic;\r
99 irdy : in std_logic;\r
100 trdy : out std_logic;\r
101 devsel : out std_logic;\r
102 stop : out std_logic;\r
103 idsel : in std_logic;\r
104 perr : out std_logic;\r
105 serr : out std_logic;\r
106 intb : out std_logic;\r
107 \r
108 -- Master whisbone\r
109 wb_adr_o : out std_logic_vector(24 downto 1); \r
110 wb_dat_i : in std_logic_vector(15 downto 0);\r
111 wb_dat_o : out std_logic_vector(15 downto 0);\r
112 wb_sel_o : out std_logic_vector(1 downto 0);\r
113 wb_we_o : out std_logic;\r
114 wb_stb_o : out std_logic;\r
115 wb_cyc_o : out std_logic;\r
116 wb_ack_i : in std_logic;\r
117 wb_err_i : in std_logic;\r
118 wb_int_i : in std_logic;\r
119\r
120 -- debug signals\r
121 debug_init : out std_logic;\r
122 debug_access : out std_logic \r
123\r
124 );\r
125end component;\r
126\r
152884e6 127component heartbeat\r
95764a11 128port (\r
152884e6 129 clk_i : in std_logic;\r
130 nrst_i : in std_logic;\r
f7be0147 131 led2_o : out std_logic;\r
132 led3_o : out std_logic;\r
133 led4_o : out std_logic;\r
36a53ce2 134 led5_o : out std_logic;\r
135 led6_o : out std_logic;\r
136 led7_o : out std_logic;\r
137 led8_o : out std_logic;\r
138 led9_o : out std_logic\r
152884e6 139);\r
95764a11 140end component;\r
141\r
142\r
143--+-----------------------------------------------------------------------------+\r
144--| CONSTANTS |\r
145--+-----------------------------------------------------------------------------+\r
146--+-----------------------------------------------------------------------------+\r
147--| SIGNALS |\r
148--+-----------------------------------------------------------------------------+\r
149\r
150 signal wb_adr : std_logic_vector(24 downto 1); \r
151 signal wb_dat_out : std_logic_vector(15 downto 0);\r
152 signal wb_dat_in : std_logic_vector(15 downto 0);\r
153 signal wb_sel : std_logic_vector(1 downto 0);\r
154 signal wb_we : std_logic;\r
155 signal wb_stb : std_logic;\r
156 signal wb_cyc : std_logic;\r
157 signal wb_ack : std_logic;\r
158 signal wb_err : std_logic;\r
159 signal wb_int : std_logic;\r
160\r
161\r
162begin\r
163\r
95764a11 164--+-----------------------------------------+\r
165--| PCI Target |\r
166--+-----------------------------------------+\r
167\r
168u_pci: component pci32tlite\r
169port map(\r
170 clk33 => PCI_CLK,\r
171 nrst => PCI_nRES,\r
172 ad => PCI_AD,\r
173 cbe => PCI_CBE,\r
174 par => PCI_PAR,\r
175 frame => PCI_nFRAME,\r
176 irdy => PCI_nIRDY,\r
177 trdy => PCI_nTRDY,\r
178 devsel => PCI_nDEVSEL,\r
179 stop => PCI_nSTOP,\r
180 idsel => PCI_IDSEL,\r
181 perr => PCI_nPERR,\r
182 serr => PCI_nSERR,\r
183 intb => PCI_nINT,\r
184 wb_adr_o => wb_adr, \r
185 wb_dat_i => wb_dat_out,\r
186 wb_dat_o => wb_dat_in,\r
187 wb_sel_o => wb_sel, \r
188 wb_we_o => wb_we,\r
189 wb_stb_o => wb_stb, \r
190 wb_cyc_o => wb_cyc,\r
191 wb_ack_i => wb_ack,\r
192 wb_err_i => wb_err,\r
f7be0147 193 wb_int_i => wb_int\r
194-- debug_init => LED3,\r
195-- debug_access => LED2\r
95764a11 196 );\r
197\r
198--+-----------------------------------------+\r
199--| WB-7seg |\r
200--+-----------------------------------------+\r
201\r
152884e6 202my_heartbeat: component heartbeat\r
203port map( \r
204 clk_i => PCI_CLK,\r
205 nrst_i => PCI_nRES,\r
f7be0147 206 led2_o => LED2,\r
207 led3_o => LED3,\r
208 led4_o => LED4,\r
36a53ce2 209 led5_o => LED5,\r
210 led6_o => IDE1,\r
211 led7_o => IDE2,\r
212 led8_o => IDE3,\r
213 led9_o => IDE4\r
95764a11 214);\r
215\r
ad16d1e3 216end raggedstone_arch;\r
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