fix chipscope signals
[raggedstone] / dhwk_old / dhwk.prj
CommitLineData
ebba63a9 1verilog work "source/sync.v"
2verilog work "source/pcidec.v"
3verilog work "source/pcidmux.v"
0e86e4be 4verilog work "source/generic_fifo_sc_a.v"
b8da6409 5verilog work "source/generic_dpram.v"
97dd6770 6verilog work "source/wb_fifo.v"
ebba63a9 7
8verilog work "source/pciwbsequ.v"
9verilog work "source/pcipargen.v"
10
11vhdl work "source/pciwbsequ.vhd"
12vhdl work "source/pfs.vhd"
13vhdl work "source/new_pciregs.vhd"
14vhdl work "source/pcipargen.vhd"
15vhdl work "source/new_pci32tlite.vhd"
16vhdl work "source/top_dhwk.vhd"
17vhdl work "source/heartbeat.vhd"
Impressum, Datenschutz