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[raggedstone] / dhwk / source / ven_rev_id.vhd
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fdb87310 1-- J.STELZNER\r
2-- INFORMATIK-3 LABOR\r
3-- 23.08.2006\r
4-- File: VEN_REV_ID.VHD\r
5\r
6library IEEE;\r
7use IEEE.std_logic_1164.all;\r
8\r
9entity VEN_REV_ID is\r
10 port\r
11 (\r
12 VEN_ID :out std_logic_vector(15 downto 0);\r
13 REV_ID :out std_logic_vector( 7 downto 0)\r
14 );\r
15end entity VEN_REV_ID;\r
16\r
17architecture VEN_REV_ID_DESIGN of VEN_REV_ID is\r
18\r
19begin\r
20\r
21 VEN_ID <= X"2222";\r
22 REV_ID <= X"01";\r
23\r
24end architecture VEN_REV_ID_DESIGN;\r
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