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+= heartbeat
[raggedstone] / heartbeat / source / top_raggedstone.vhd
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CommitLineData
1--+-------------------------------------------------------------------------------------------------+\r
2--| |\r
3--| File: top.vhd |\r
4--| |\r
5--| Components: pci32lite.vhd |\r
6--| pciwbsequ.vhd |\r
7--| pcidmux.vhd |\r
8--| pciregs.vhd |\r
9--| pcipargen.vhd |\r
10--| -- Libs -- |\r
11--| ona.vhd |\r
12--| |\r
13--| Description: RS1 PCI Demo : (TOP) Main file. |\r
14--| |\r
15--| |\r
16--| |\r
17--+-------------------------------------------------------------------------------------------------+\r
18--| |\r
19--| Revision history : |\r
20--| Date Version Author Description |\r
21--| |\r
22--| |\r
23--| To do: |\r
24--| |\r
25--+-------------------------------------------------------------------------------------------------+\r
26\r
27\r
28--+-----------------------------------------------------------------------------+\r
29--| LIBRARIES |\r
30--+-----------------------------------------------------------------------------+\r
31\r
32library ieee;\r
33use ieee.std_logic_1164.all;\r
34use ieee.std_logic_arith.all;\r
35use ieee.std_logic_unsigned.all;\r
36\r
37--+-----------------------------------------------------------------------------+\r
38--| ENTITY |\r
39--+-----------------------------------------------------------------------------+\r
40\r
41entity pci_7seg is\r
42port (\r
43\r
44 -- General \r
45 PCI_CLK : in std_logic;\r
46 PCI_nRES : in std_logic;\r
47 \r
48 -- PCI target 32bits\r
49 PCI_AD : inout std_logic_vector(31 downto 0);\r
50 PCI_CBE : in std_logic_vector(3 downto 0);\r
51 PCI_PAR : out std_logic; \r
52 PCI_nFRAME : in std_logic;\r
53 PCI_nIRDY : in std_logic;\r
54 PCI_nTRDY : out std_logic;\r
55 PCI_nDEVSEL : out std_logic;\r
56 PCI_nSTOP : out std_logic;\r
57 PCI_IDSEL : in std_logic;\r
58 PCI_nPERR : out std_logic;\r
59 PCI_nSERR : out std_logic;\r
60 PCI_nINT : out std_logic;\r
61 \r
62 -- debug signals\r
63 LED_INIT : out std_logic;\r
64 LED_ACCESS : out std_logic;\r
65 LED_ALIVE : out std_logic\r
66\r
67);\r
68end pci_7seg;\r
69\r
70\r
71--+-----------------------------------------------------------------------------+\r
72--| ARCHITECTURE |\r
73--+-----------------------------------------------------------------------------+\r
74\r
75architecture pci_7seg_arch of pci_7seg is\r
76\r
77\r
78--+-----------------------------------------------------------------------------+\r
79--| COMPONENTS |\r
80--+-----------------------------------------------------------------------------+\r
81\r
82component pci32tlite\r
83port (\r
84\r
85 -- General \r
86 clk33 : in std_logic;\r
87 nrst : in std_logic;\r
88 \r
89 -- PCI target 32bits\r
90 ad : inout std_logic_vector(31 downto 0);\r
91 cbe : in std_logic_vector(3 downto 0);\r
92 par : out std_logic; \r
93 frame : in std_logic;\r
94 irdy : in std_logic;\r
95 trdy : out std_logic;\r
96 devsel : out std_logic;\r
97 stop : out std_logic;\r
98 idsel : in std_logic;\r
99 perr : out std_logic;\r
100 serr : out std_logic;\r
101 intb : out std_logic;\r
102 \r
103 -- Master whisbone\r
104 wb_adr_o : out std_logic_vector(24 downto 1); \r
105 wb_dat_i : in std_logic_vector(15 downto 0);\r
106 wb_dat_o : out std_logic_vector(15 downto 0);\r
107 wb_sel_o : out std_logic_vector(1 downto 0);\r
108 wb_we_o : out std_logic;\r
109 wb_stb_o : out std_logic;\r
110 wb_cyc_o : out std_logic;\r
111 wb_ack_i : in std_logic;\r
112 wb_err_i : in std_logic;\r
113 wb_int_i : in std_logic;\r
114\r
115 -- debug signals\r
116 debug_init : out std_logic;\r
117 debug_access : out std_logic \r
118\r
119 );\r
120end component;\r
121\r
122component heartbeat\r
123port (\r
124 clk_i : in std_logic;\r
125 nrst_i : in std_logic;\r
126 led_o : out std_logic\r
127);\r
128end component;\r
129\r
130\r
131--+-----------------------------------------------------------------------------+\r
132--| CONSTANTS |\r
133--+-----------------------------------------------------------------------------+\r
134--+-----------------------------------------------------------------------------+\r
135--| SIGNALS |\r
136--+-----------------------------------------------------------------------------+\r
137\r
138 signal wb_adr : std_logic_vector(24 downto 1); \r
139 signal wb_dat_out : std_logic_vector(15 downto 0);\r
140 signal wb_dat_in : std_logic_vector(15 downto 0);\r
141 signal wb_sel : std_logic_vector(1 downto 0);\r
142 signal wb_we : std_logic;\r
143 signal wb_stb : std_logic;\r
144 signal wb_cyc : std_logic;\r
145 signal wb_ack : std_logic;\r
146 signal wb_err : std_logic;\r
147 signal wb_int : std_logic;\r
148\r
149\r
150begin\r
151\r
152--+-----------------------------------------+\r
153--| PCI Target |\r
154--+-----------------------------------------+\r
155\r
156u_pci: component pci32tlite\r
157port map(\r
158 clk33 => PCI_CLK,\r
159 nrst => PCI_nRES,\r
160 ad => PCI_AD,\r
161 cbe => PCI_CBE,\r
162 par => PCI_PAR,\r
163 frame => PCI_nFRAME,\r
164 irdy => PCI_nIRDY,\r
165 trdy => PCI_nTRDY,\r
166 devsel => PCI_nDEVSEL,\r
167 stop => PCI_nSTOP,\r
168 idsel => PCI_IDSEL,\r
169 perr => PCI_nPERR,\r
170 serr => PCI_nSERR,\r
171 intb => PCI_nINT,\r
172 wb_adr_o => wb_adr, \r
173 wb_dat_i => wb_dat_out,\r
174 wb_dat_o => wb_dat_in,\r
175 wb_sel_o => wb_sel, \r
176 wb_we_o => wb_we,\r
177 wb_stb_o => wb_stb, \r
178 wb_cyc_o => wb_cyc,\r
179 wb_ack_i => wb_ack,\r
180 wb_err_i => wb_err,\r
181 wb_int_i => wb_int,\r
182 debug_init => LED_INIT,\r
183 debug_access => LED_ACCESS\r
184 );\r
185\r
186--+-----------------------------------------+\r
187--| WB-7seg |\r
188--+-----------------------------------------+\r
189\r
190my_heartbeat: component heartbeat\r
191port map( \r
192 clk_i => PCI_CLK,\r
193 nrst_i => PCI_nRES,\r
194 led_o => LED_ALIVE\r
195);\r
196\r
197end pci_7seg_arch;\r
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