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1 | ////////////////////////////////////////////////////////////////////// | |
2 | //// //// | |
3 | //// eth_txethmac.v //// | |
4 | /// //// | |
5 | //// This file is part of the Ethernet IP core project //// | |
6 | //// http://www.opencores.org/projects/ethmac/ //// | |
7 | //// //// | |
8 | //// Author(s): //// | |
9 | //// - Igor Mohor (igorM@opencores.org) //// | |
10 | //// - Novan Hartadi (novan@vlsi.itb.ac.id) //// | |
11 | //// - Mahmud Galela (mgalela@vlsi.itb.ac.id) //// | |
12 | //// //// | |
13 | //// All additional information is avaliable in the Readme.txt //// | |
14 | //// file. //// | |
15 | //// //// | |
16 | ////////////////////////////////////////////////////////////////////// | |
17 | //// //// | |
18 | //// Copyright (C) 2001 Authors //// | |
19 | //// //// | |
20 | //// This source file may be used and distributed without //// | |
21 | //// restriction provided that this copyright statement is not //// | |
22 | //// removed from the file and that any derivative work contains //// | |
23 | //// the original copyright notice and the associated disclaimer. //// | |
24 | //// //// | |
25 | //// This source file is free software; you can redistribute it //// | |
26 | //// and/or modify it under the terms of the GNU Lesser General //// | |
27 | //// Public License as published by the Free Software Foundation; //// | |
28 | //// either version 2.1 of the License, or (at your option) any //// | |
29 | //// later version. //// | |
30 | //// //// | |
31 | //// This source is distributed in the hope that it will be //// | |
32 | //// useful, but WITHOUT ANY WARRANTY; without even the implied //// | |
33 | //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// | |
34 | //// PURPOSE. See the GNU Lesser General Public License for more //// | |
35 | //// details. //// | |
36 | //// //// | |
37 | //// You should have received a copy of the GNU Lesser General //// | |
38 | //// Public License along with this source; if not, download it //// | |
39 | //// from http://www.opencores.org/lgpl.shtml //// | |
40 | //// //// | |
41 | ////////////////////////////////////////////////////////////////////// | |
42 | // | |
43 | // CVS Revision History | |
44 | // | |
45 | // $Log: eth_txethmac.v,v $ | |
46 | // Revision 1.1 2007-03-20 17:50:56 sithglan | |
47 | // add shit | |
48 | // | |
49 | // Revision 1.9 2005/02/21 11:25:28 igorm | |
50 | // Delayed CRC fixed. | |
51 | // | |
52 | // Revision 1.8 2003/01/30 13:33:24 mohor | |
53 | // When padding was enabled and crc disabled, frame was not ended correctly. | |
54 | // | |
55 | // Revision 1.7 2002/02/26 16:24:01 mohor | |
56 | // RetryCntLatched was unused and removed from design | |
57 | // | |
58 | // Revision 1.6 2002/02/22 12:56:35 mohor | |
59 | // Retry is not activated when a Tx Underrun occured | |
60 | // | |
61 | // Revision 1.5 2002/02/11 09:18:22 mohor | |
62 | // Tx status is written back to the BD. | |
63 | // | |
64 | // Revision 1.4 2002/01/23 10:28:16 mohor | |
65 | // Link in the header changed. | |
66 | // | |
67 | // Revision 1.3 2001/10/19 08:43:51 mohor | |
68 | // eth_timescale.v changed to timescale.v This is done because of the | |
69 | // simulation of the few cores in a one joined project. | |
70 | // | |
71 | // Revision 1.2 2001/09/11 14:17:00 mohor | |
72 | // Few little NCSIM warnings fixed. | |
73 | // | |
74 | // Revision 1.1 2001/08/06 14:44:29 mohor | |
75 | // A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex). | |
76 | // Include files fixed to contain no path. | |
77 | // File names and module names changed ta have a eth_ prologue in the name. | |
78 | // File eth_timescale.v is used to define timescale | |
79 | // All pin names on the top module are changed to contain _I, _O or _OE at the end. | |
80 | // Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O | |
81 | // and Mdo_OE. The bidirectional signal must be created on the top level. This | |
82 | // is done due to the ASIC tools. | |
83 | // | |
84 | // Revision 1.1 2001/07/30 21:23:42 mohor | |
85 | // Directory structure changed. Files checked and joind together. | |
86 | // | |
87 | // Revision 1.3 2001/06/19 18:16:40 mohor | |
88 | // TxClk changed to MTxClk (as discribed in the documentation). | |
89 | // Crc changed so only one file can be used instead of two. | |
90 | // | |
91 | // Revision 1.2 2001/06/19 10:38:08 mohor | |
92 | // Minor changes in header. | |
93 | // | |
94 | // Revision 1.1 2001/06/19 10:27:58 mohor | |
95 | // TxEthMAC initial release. | |
96 | // | |
97 | // | |
98 | // | |
99 | ||
100 | `include "timescale.v" | |
101 | ||
102 | ||
103 | module eth_txethmac (MTxClk, Reset, TxStartFrm, TxEndFrm, TxUnderRun, TxData, CarrierSense, | |
104 | Collision, Pad, CrcEn, FullD, HugEn, DlyCrcEn, MinFL, MaxFL, IPGT, | |
105 | IPGR1, IPGR2, CollValid, MaxRet, NoBckof, ExDfrEn, | |
106 | MTxD, MTxEn, MTxErr, TxDone, TxRetry, TxAbort, TxUsedData, WillTransmit, | |
107 | ResetCollision, RetryCnt, StartTxDone, StartTxAbort, MaxCollisionOccured, | |
108 | LateCollision, DeferIndication, StatePreamble, StateData | |
109 | ||
110 | ); | |
111 | ||
112 | parameter Tp = 1; | |
113 | ||
114 | ||
115 | input MTxClk; // Transmit clock (from PHY) | |
116 | input Reset; // Reset | |
117 | input TxStartFrm; // Transmit packet start frame | |
118 | input TxEndFrm; // Transmit packet end frame | |
119 | input TxUnderRun; // Transmit packet under-run | |
120 | input [7:0] TxData; // Transmit packet data byte | |
121 | input CarrierSense; // Carrier sense (synchronized) | |
122 | input Collision; // Collision (synchronized) | |
123 | input Pad; // Pad enable (from register) | |
124 | input CrcEn; // Crc enable (from register) | |
125 | input FullD; // Full duplex (from register) | |
126 | input HugEn; // Huge packets enable (from register) | |
127 | input DlyCrcEn; // Delayed Crc enabled (from register) | |
128 | input [15:0] MinFL; // Minimum frame length (from register) | |
129 | input [15:0] MaxFL; // Maximum frame length (from register) | |
130 | input [6:0] IPGT; // Back to back transmit inter packet gap parameter (from register) | |
131 | input [6:0] IPGR1; // Non back to back transmit inter packet gap parameter IPGR1 (from register) | |
132 | input [6:0] IPGR2; // Non back to back transmit inter packet gap parameter IPGR2 (from register) | |
133 | input [5:0] CollValid; // Valid collision window (from register) | |
134 | input [3:0] MaxRet; // Maximum retry number (from register) | |
135 | input NoBckof; // No backoff (from register) | |
136 | input ExDfrEn; // Excessive defferal enable (from register) | |
137 | ||
138 | output [3:0] MTxD; // Transmit nibble (to PHY) | |
139 | output MTxEn; // Transmit enable (to PHY) | |
140 | output MTxErr; // Transmit error (to PHY) | |
141 | output TxDone; // Transmit packet done (to RISC) | |
142 | output TxRetry; // Transmit packet retry (to RISC) | |
143 | output TxAbort; // Transmit packet abort (to RISC) | |
144 | output TxUsedData; // Transmit packet used data (to RISC) | |
145 | output WillTransmit; // Will transmit (to RxEthMAC) | |
146 | output ResetCollision; // Reset Collision (for synchronizing collision) | |
147 | output [3:0] RetryCnt; // Latched Retry Counter for tx status purposes | |
148 | output StartTxDone; | |
149 | output StartTxAbort; | |
150 | output MaxCollisionOccured; | |
151 | output LateCollision; | |
152 | output DeferIndication; | |
153 | output StatePreamble; | |
154 | output [1:0] StateData; | |
155 | ||
156 | reg [3:0] MTxD; | |
157 | reg MTxEn; | |
158 | reg MTxErr; | |
159 | reg TxDone; | |
160 | reg TxRetry; | |
161 | reg TxAbort; | |
162 | reg TxUsedData; | |
163 | reg WillTransmit; | |
164 | reg ColWindow; | |
165 | reg StopExcessiveDeferOccured; | |
166 | reg [3:0] RetryCnt; | |
167 | reg [3:0] MTxD_d; | |
168 | reg StatusLatch; | |
169 | reg PacketFinished_q; | |
170 | reg PacketFinished; | |
171 | ||
172 | ||
173 | wire ExcessiveDeferOccured; | |
174 | wire StartIPG; | |
175 | wire StartPreamble; | |
176 | wire [1:0] StartData; | |
177 | wire StartFCS; | |
178 | wire StartJam; | |
179 | wire StartDefer; | |
180 | wire StartBackoff; | |
181 | wire StateDefer; | |
182 | wire StateIPG; | |
183 | wire StateIdle; | |
184 | wire StatePAD; | |
185 | wire StateFCS; | |
186 | wire StateJam; | |
187 | wire StateJam_q; | |
188 | wire StateBackOff; | |
189 | wire StateSFD; | |
190 | wire StartTxRetry; | |
191 | wire UnderRun; | |
192 | wire TooBig; | |
193 | wire [31:0] Crc; | |
194 | wire CrcError; | |
195 | wire [2:0] DlyCrcCnt; | |
196 | wire [15:0] NibCnt; | |
197 | wire NibCntEq7; | |
198 | wire NibCntEq15; | |
199 | wire NibbleMinFl; | |
200 | wire ExcessiveDefer; | |
201 | wire [15:0] ByteCnt; | |
202 | wire MaxFrame; | |
203 | wire RetryMax; | |
204 | wire RandomEq0; | |
205 | wire RandomEqByteCnt; | |
206 | wire PacketFinished_d; | |
207 | ||
208 | ||
209 | ||
210 | assign ResetCollision = ~(StatePreamble | (|StateData) | StatePAD | StateFCS); | |
211 | ||
212 | assign ExcessiveDeferOccured = TxStartFrm & StateDefer & ExcessiveDefer & ~StopExcessiveDeferOccured; | |
213 | ||
214 | assign StartTxDone = ~Collision & (StateFCS & NibCntEq7 | StateData[1] & TxEndFrm & (~Pad | Pad & NibbleMinFl) & ~CrcEn); | |
215 | ||
216 | assign UnderRun = StateData[0] & TxUnderRun & ~Collision; | |
217 | ||
218 | assign TooBig = ~Collision & MaxFrame & (StateData[0] & ~TxUnderRun | StateFCS); | |
219 | ||
220 | // assign StartTxRetry = StartJam & (ColWindow & ~RetryMax); | |
221 | assign StartTxRetry = StartJam & (ColWindow & ~RetryMax) & ~UnderRun; | |
222 | ||
223 | assign LateCollision = StartJam & ~ColWindow & ~UnderRun; | |
224 | ||
225 | assign MaxCollisionOccured = StartJam & ColWindow & RetryMax; | |
226 | ||
227 | assign StateSFD = StatePreamble & NibCntEq15; | |
228 | ||
229 | assign StartTxAbort = TooBig | UnderRun | ExcessiveDeferOccured | LateCollision | MaxCollisionOccured; | |
230 | ||
231 | ||
232 | // StopExcessiveDeferOccured | |
233 | always @ (posedge MTxClk or posedge Reset) | |
234 | begin | |
235 | if(Reset) | |
236 | StopExcessiveDeferOccured <= #Tp 1'b0; | |
237 | else | |
238 | begin | |
239 | if(~TxStartFrm) | |
240 | StopExcessiveDeferOccured <= #Tp 1'b0; | |
241 | else | |
242 | if(ExcessiveDeferOccured) | |
243 | StopExcessiveDeferOccured <= #Tp 1'b1; | |
244 | end | |
245 | end | |
246 | ||
247 | ||
248 | // Collision Window | |
249 | always @ (posedge MTxClk or posedge Reset) | |
250 | begin | |
251 | if(Reset) | |
252 | ColWindow <= #Tp 1'b1; | |
253 | else | |
254 | begin | |
255 | if(~Collision & ByteCnt[5:0] == CollValid[5:0] & (StateData[1] | StatePAD & NibCnt[0] | StateFCS & NibCnt[0])) | |
256 | ColWindow <= #Tp 1'b0; | |
257 | else | |
258 | if(StateIdle | StateIPG) | |
259 | ColWindow <= #Tp 1'b1; | |
260 | end | |
261 | end | |
262 | ||
263 | ||
264 | // Start Window | |
265 | always @ (posedge MTxClk or posedge Reset) | |
266 | begin | |
267 | if(Reset) | |
268 | StatusLatch <= #Tp 1'b0; | |
269 | else | |
270 | begin | |
271 | if(~TxStartFrm) | |
272 | StatusLatch <= #Tp 1'b0; | |
273 | else | |
274 | if(ExcessiveDeferOccured | StateIdle) | |
275 | StatusLatch <= #Tp 1'b1; | |
276 | end | |
277 | end | |
278 | ||
279 | ||
280 | // Transmit packet used data | |
281 | always @ (posedge MTxClk or posedge Reset) | |
282 | begin | |
283 | if(Reset) | |
284 | TxUsedData <= #Tp 1'b0; | |
285 | else | |
286 | TxUsedData <= #Tp |StartData; | |
287 | end | |
288 | ||
289 | ||
290 | // Transmit packet done | |
291 | always @ (posedge MTxClk or posedge Reset) | |
292 | begin | |
293 | if(Reset) | |
294 | TxDone <= #Tp 1'b0; | |
295 | else | |
296 | begin | |
297 | if(TxStartFrm & ~StatusLatch) | |
298 | TxDone <= #Tp 1'b0; | |
299 | else | |
300 | if(StartTxDone) | |
301 | TxDone <= #Tp 1'b1; | |
302 | end | |
303 | end | |
304 | ||
305 | ||
306 | // Transmit packet retry | |
307 | always @ (posedge MTxClk or posedge Reset) | |
308 | begin | |
309 | if(Reset) | |
310 | TxRetry <= #Tp 1'b0; | |
311 | else | |
312 | begin | |
313 | if(TxStartFrm & ~StatusLatch) | |
314 | TxRetry <= #Tp 1'b0; | |
315 | else | |
316 | if(StartTxRetry) | |
317 | TxRetry <= #Tp 1'b1; | |
318 | end | |
319 | end | |
320 | ||
321 | ||
322 | // Transmit packet abort | |
323 | always @ (posedge MTxClk or posedge Reset) | |
324 | begin | |
325 | if(Reset) | |
326 | TxAbort <= #Tp 1'b0; | |
327 | else | |
328 | begin | |
329 | if(TxStartFrm & ~StatusLatch & ~ExcessiveDeferOccured) | |
330 | TxAbort <= #Tp 1'b0; | |
331 | else | |
332 | if(StartTxAbort) | |
333 | TxAbort <= #Tp 1'b1; | |
334 | end | |
335 | end | |
336 | ||
337 | ||
338 | // Retry counter | |
339 | always @ (posedge MTxClk or posedge Reset) | |
340 | begin | |
341 | if(Reset) | |
342 | RetryCnt[3:0] <= #Tp 4'h0; | |
343 | else | |
344 | begin | |
345 | if(ExcessiveDeferOccured | UnderRun | TooBig | StartTxDone | TxUnderRun | |
346 | | StateJam & NibCntEq7 & (~ColWindow | RetryMax)) | |
347 | RetryCnt[3:0] <= #Tp 4'h0; | |
348 | else | |
349 | if(StateJam & NibCntEq7 & ColWindow & (RandomEq0 | NoBckof) | StateBackOff & RandomEqByteCnt) | |
350 | RetryCnt[3:0] <= #Tp RetryCnt[3:0] + 1'b1; | |
351 | end | |
352 | end | |
353 | ||
354 | ||
355 | assign RetryMax = RetryCnt[3:0] == MaxRet[3:0]; | |
356 | ||
357 | ||
358 | // Transmit nibble | |
359 | always @ (StatePreamble or StateData or StateData or StateFCS or StateJam or StateSFD or TxData or | |
360 | Crc or NibCntEq15) | |
361 | begin | |
362 | if(StateData[0]) | |
363 | MTxD_d[3:0] = TxData[3:0]; // Lower nibble | |
364 | else | |
365 | if(StateData[1]) | |
366 | MTxD_d[3:0] = TxData[7:4]; // Higher nibble | |
367 | else | |
368 | if(StateFCS) | |
369 | MTxD_d[3:0] = {~Crc[28], ~Crc[29], ~Crc[30], ~Crc[31]}; // Crc | |
370 | else | |
371 | if(StateJam) | |
372 | MTxD_d[3:0] = 4'h9; // Jam pattern | |
373 | else | |
374 | if(StatePreamble) | |
375 | if(NibCntEq15) | |
376 | MTxD_d[3:0] = 4'hd; // SFD | |
377 | else | |
378 | MTxD_d[3:0] = 4'h5; // Preamble | |
379 | else | |
380 | MTxD_d[3:0] = 4'h0; | |
381 | end | |
382 | ||
383 | ||
384 | // Transmit Enable | |
385 | always @ (posedge MTxClk or posedge Reset) | |
386 | begin | |
387 | if(Reset) | |
388 | MTxEn <= #Tp 1'b0; | |
389 | else | |
390 | MTxEn <= #Tp StatePreamble | (|StateData) | StatePAD | StateFCS | StateJam; | |
391 | end | |
392 | ||
393 | ||
394 | // Transmit nibble | |
395 | always @ (posedge MTxClk or posedge Reset) | |
396 | begin | |
397 | if(Reset) | |
398 | MTxD[3:0] <= #Tp 4'h0; | |
399 | else | |
400 | MTxD[3:0] <= #Tp MTxD_d[3:0]; | |
401 | end | |
402 | ||
403 | ||
404 | // Transmit error | |
405 | always @ (posedge MTxClk or posedge Reset) | |
406 | begin | |
407 | if(Reset) | |
408 | MTxErr <= #Tp 1'b0; | |
409 | else | |
410 | MTxErr <= #Tp TooBig | UnderRun; | |
411 | end | |
412 | ||
413 | ||
414 | // WillTransmit | |
415 | always @ (posedge MTxClk or posedge Reset) | |
416 | begin | |
417 | if(Reset) | |
418 | WillTransmit <= #Tp 1'b0; | |
419 | else | |
420 | WillTransmit <= #Tp StartPreamble | StatePreamble | (|StateData) | StatePAD | StateFCS | StateJam; | |
421 | end | |
422 | ||
423 | ||
424 | assign PacketFinished_d = StartTxDone | TooBig | UnderRun | LateCollision | MaxCollisionOccured | ExcessiveDeferOccured; | |
425 | ||
426 | ||
427 | // Packet finished | |
428 | always @ (posedge MTxClk or posedge Reset) | |
429 | begin | |
430 | if(Reset) | |
431 | begin | |
432 | PacketFinished <= #Tp 1'b0; | |
433 | PacketFinished_q <= #Tp 1'b0; | |
434 | end | |
435 | else | |
436 | begin | |
437 | PacketFinished <= #Tp PacketFinished_d; | |
438 | PacketFinished_q <= #Tp PacketFinished; | |
439 | end | |
440 | end | |
441 | ||
442 | ||
443 | // Connecting module Counters | |
444 | eth_txcounters txcounters1 (.StatePreamble(StatePreamble), .StateIPG(StateIPG), .StateData(StateData), | |
445 | .StatePAD(StatePAD), .StateFCS(StateFCS), .StateJam(StateJam), .StateBackOff(StateBackOff), | |
446 | .StateDefer(StateDefer), .StateIdle(StateIdle), .StartDefer(StartDefer), .StartIPG(StartIPG), | |
447 | .StartFCS(StartFCS), .StartJam(StartJam), .TxStartFrm(TxStartFrm), .MTxClk(MTxClk), | |
448 | .Reset(Reset), .MinFL(MinFL), .MaxFL(MaxFL), .HugEn(HugEn), .ExDfrEn(ExDfrEn), | |
449 | .PacketFinished_q(PacketFinished_q), .DlyCrcEn(DlyCrcEn), .StartBackoff(StartBackoff), | |
450 | .StateSFD(StateSFD), .ByteCnt(ByteCnt), .NibCnt(NibCnt), .ExcessiveDefer(ExcessiveDefer), | |
451 | .NibCntEq7(NibCntEq7), .NibCntEq15(NibCntEq15), .MaxFrame(MaxFrame), .NibbleMinFl(NibbleMinFl), | |
452 | .DlyCrcCnt(DlyCrcCnt) | |
453 | ); | |
454 | ||
455 | ||
456 | // Connecting module StateM | |
457 | eth_txstatem txstatem1 (.MTxClk(MTxClk), .Reset(Reset), .ExcessiveDefer(ExcessiveDefer), .CarrierSense(CarrierSense), | |
458 | .NibCnt(NibCnt[6:0]), .IPGT(IPGT), .IPGR1(IPGR1), .IPGR2(IPGR2), .FullD(FullD), | |
459 | .TxStartFrm(TxStartFrm), .TxEndFrm(TxEndFrm), .TxUnderRun(TxUnderRun), .Collision(Collision), | |
460 | .UnderRun(UnderRun), .StartTxDone(StartTxDone), .TooBig(TooBig), .NibCntEq7(NibCntEq7), | |
461 | .NibCntEq15(NibCntEq15), .MaxFrame(MaxFrame), .Pad(Pad), .CrcEn(CrcEn), | |
462 | .NibbleMinFl(NibbleMinFl), .RandomEq0(RandomEq0), .ColWindow(ColWindow), .RetryMax(RetryMax), | |
463 | .NoBckof(NoBckof), .RandomEqByteCnt(RandomEqByteCnt), .StateIdle(StateIdle), | |
464 | .StateIPG(StateIPG), .StatePreamble(StatePreamble), .StateData(StateData), .StatePAD(StatePAD), | |
465 | .StateFCS(StateFCS), .StateJam(StateJam), .StateJam_q(StateJam_q), .StateBackOff(StateBackOff), | |
466 | .StateDefer(StateDefer), .StartFCS(StartFCS), .StartJam(StartJam), .StartBackoff(StartBackoff), | |
467 | .StartDefer(StartDefer), .DeferIndication(DeferIndication), .StartPreamble(StartPreamble), .StartData(StartData), .StartIPG(StartIPG) | |
468 | ); | |
469 | ||
470 | ||
471 | wire Enable_Crc; | |
472 | wire [3:0] Data_Crc; | |
473 | wire Initialize_Crc; | |
474 | ||
475 | assign Enable_Crc = ~StateFCS; | |
476 | ||
477 | assign Data_Crc[0] = StateData[0]? TxData[3] : StateData[1]? TxData[7] : 1'b0; | |
478 | assign Data_Crc[1] = StateData[0]? TxData[2] : StateData[1]? TxData[6] : 1'b0; | |
479 | assign Data_Crc[2] = StateData[0]? TxData[1] : StateData[1]? TxData[5] : 1'b0; | |
480 | assign Data_Crc[3] = StateData[0]? TxData[0] : StateData[1]? TxData[4] : 1'b0; | |
481 | ||
482 | assign Initialize_Crc = StateIdle | StatePreamble | (|DlyCrcCnt); | |
483 | ||
484 | ||
485 | // Connecting module Crc | |
486 | eth_crc txcrc (.Clk(MTxClk), .Reset(Reset), .Data(Data_Crc), .Enable(Enable_Crc), .Initialize(Initialize_Crc), | |
487 | .Crc(Crc), .CrcError(CrcError) | |
488 | ); | |
489 | ||
490 | ||
491 | // Connecting module Random | |
492 | eth_random random1 (.MTxClk(MTxClk), .Reset(Reset), .StateJam(StateJam), .StateJam_q(StateJam_q), .RetryCnt(RetryCnt), | |
493 | .NibCnt(NibCnt), .ByteCnt(ByteCnt[9:0]), .RandomEq0(RandomEq0), .RandomEqByteCnt(RandomEqByteCnt)); | |
494 | ||
495 | ||
496 | ||
497 | ||
498 | endmodule |