revert PCI_CLOCK in heartbeat project

[raggedstone] / dhwk / source / pci / parity_out.vhd

-- J.STELZNER
-- INFORMATIK-3 LABOR
-- 23.08.2006
-- File: PARITY_OUT.VHD

library ieee;
use ieee.std_logic_1164.all;

entity PARITY_OUT is
        port(
                    PCI_CLOCK :in std_logic;
                    PCI_RSTn :in std_logic;
                    PAR_IN :in std_logic_vector ( 2 downto 0);
                    PAR_REG :in std_logic;
                    SERR_CHECK :in std_logic;
                    PERR_CHECK :in std_logic;
                    OE_PCI_PAR :in std_logic;
                    OE_PCI_PERR :in std_logic;
                    PA_ER_RE :in std_logic;
                    SERR_ENA :in std_logic;
                    PCI_PAR_IN :in std_logic;
                    PERR :out std_logic;
                    SERR :out std_logic;
                    PCI_PERRn :out std_logic; -- s/t/s
                    PCI_SERRn :out std_logic; -- o/d
                    PCI_PAR :out std_logic -- t/s
            );
end entity PARITY_OUT;

architecture PARITY_OUT_DESIGN of PARITY_OUT is

        signal PAR :std_logic;
        signal PAR_FF :std_logic;
        signal SERR_FF :std_logic;
        signal PERR_FF :std_logic;

begin

        PAR <= ( PAR_IN(2) xor PAR_IN(1) xor PAR_IN(0) );

        process (PCI_CLOCK, PCI_RSTn)
        begin
        if PCI_RSTn = '0' then PAR_FF <= '0';
                PERR_FF <= '0';
                SERR_FF <= '0';

        elsif (rising_edge(PCI_CLOCK)) then
                SERR_FF <= ((PCI_PAR_IN xor PAR) and SERR_CHECK) and PA_ER_RE and SERR_ENA and (not SERR_FF);
                PERR_FF <= ((PCI_PAR_IN xor PAR) and PERR_CHECK) and (not PERR_FF);
        end if;
end process;

SERR <= SERR_FF;
PERR <= PERR_FF;

PCI_PAR <= PAR_FF when OE_PCI_PAR = '1' else 'Z';
PCI_SERRn <= '0' when SERR_FF = '1' else 'Z';
PCI_PERRn <= not PERR_FF when OE_PCI_PERR = '1' and PA_ER_RE = '1' else 'Z';

end architecture PARITY_OUT_DESIGN;