]> git.zerfleddert.de Git - raggedstone/blame_incremental - dhwk/source/top.vhd
projects / raggedstone / blame_incremental
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (non-incremental) | history | HEAD
CBEn
[raggedstone] / dhwk / source / top.vhd
... / ...
CommitLineData
1-- VHDL model created from schematic top.sch -- Jan 09 20:54:18 2007\r
2\r
3\r
4\r
5LIBRARY ieee;\r
6\r
7USE ieee.std_logic_1164.ALL;\r
8USE ieee.numeric_std.ALL;\r
9\r
10\r
11entity dhwk is\r
12 Port ( KONST_1 : In std_logic;\r
13 PCI_CBEn : In std_logic_vector (3 downto 0);\r
14 PCI_CLOCK : In std_logic;\r
15 PCI_FRAMEn : In std_logic;\r
16 PCI_IDSEL : In std_logic;\r
17 PCI_IRDYn : In std_logic;\r
18 PCI_RSTn : In std_logic;\r
19-- SERIAL_IN : In std_logic;\r
20-- SPC_RDY_IN : In std_logic;\r
21 TAST_RESn : In std_logic;\r
22 TAST_SETn : In std_logic;\r
23 LED_2 : out std_logic;\r
24 LED_3 : out std_logic;\r
25 LED_4 : out std_logic;\r
26 LED_5 : out std_logic;\r
27 PCI_AD : InOut std_logic_vector (31 downto 0);\r
28 PCI_PAR : InOut std_logic;\r
29 PCI_DEVSELn : Out std_logic;\r
30 PCI_INTAn : Out std_logic;\r
31 PCI_PERRn : Out std_logic;\r
32 PCI_SERRn : Out std_logic;\r
33 PCI_STOPn : Out std_logic;\r
34 PCI_TRDYn : Out std_logic;\r
35-- SERIAL_OUT : Out std_logic;\r
36-- SPC_RDY_OUT : Out std_logic;\r
37 TB_IDSEL : Out std_logic;\r
38 TB_nDEVSEL : Out std_logic;\r
39 TB_nINTA : Out std_logic );\r
40end dhwk;\r
41\r
42architecture SCHEMATIC of dhwk is\r
43\r
44 SIGNAL gnd : std_logic := '0';\r
45 SIGNAL vcc : std_logic := '1';\r
46\r
47 signal READ_XX7_6 : std_logic;\r
48 signal RESERVE : std_logic;\r
49 signal SR_ERROR : std_logic;\r
50 signal R_ERROR : std_logic;\r
51 signal S_ERROR : std_logic;\r
52 signal WRITE_XX3_2 : std_logic;\r
53 signal WRITE_XX5_4 : std_logic;\r
54 signal WRITE_XX7_6 : std_logic;\r
55 signal READ_XX1_0 : std_logic;\r
56 signal READ_XX3_2 : std_logic;\r
57 signal INTAn : std_logic;\r
58 signal TRDYn : std_logic;\r
59 signal READ_XX5_4 : std_logic;\r
60 signal DEVSELn : std_logic;\r
61 signal FIFO_RDn : std_logic;\r
62 signal WRITE_XX1_0 : std_logic;\r
63 signal REG_OUT_XX6 : std_logic_vector (7 downto 0);\r
64 signal SYNC_FLAG : std_logic_vector (7 downto 0);\r
65 signal INT_REG : std_logic_vector (7 downto 0);\r
66 signal REVISON_ID : std_logic_vector (7 downto 0);\r
67 signal VENDOR_ID : std_logic_vector (15 downto 0);\r
68 signal READ_SEL : std_logic_vector (1 downto 0);\r
69 signal AD_REG : std_logic_vector (31 downto 0);\r
70 signal REG_OUT_XX7 : std_logic_vector (7 downto 0);\r
71 signal R_EFn : std_logic;\r
72 signal R_FFn : std_logic;\r
73 signal R_FIFO_Q_OUT : std_logic_vector (7 downto 0);\r
74 signal R_HFn : std_logic;\r
75 signal S_EFn : std_logic;\r
76 signal S_FFn : std_logic;\r
77 signal S_FIFO_Q_OUT : std_logic_vector (7 downto 0);\r
78 signal S_HFn : std_logic;\r
79 signal R_FIFO_D_IN : std_logic_vector (7 downto 0);\r
80 signal R_FIFO_READn : std_logic;\r
81 signal R_FIFO_RESETn : std_logic;\r
82 signal R_FIFO_RTn : std_logic;\r
83 signal R_FIFO_WRITEn : std_logic;\r
84 signal S_FIFO_D_IN : std_logic_vector (7 downto 0);\r
85 signal S_FIFO_READn : std_logic;\r
86 signal S_FIFO_RESETn : std_logic;\r
87 signal S_FIFO_RTn : std_logic;\r
88 signal S_FIFO_WRITEn : std_logic;\r
89 signal SERIAL_IN : std_logic;\r
90 signal SPC_RDY_IN : std_logic;\r
91 signal SERIAL_OUT : std_logic;\r
92 signal SPC_RDY_OUT : std_logic;\r
93 signal watch : std_logic;\r
94 signal control0 : std_logic_vector(35 downto 0);\r
95 signal data : std_logic_vector(95 downto 0);\r
96 signal trig0 : std_logic_vector(31 downto 0);\r
97\r
98 component MESS_1_TB\r
99 Port ( DEVSELn : In std_logic;\r
100 INTAn : In std_logic;\r
101 KONST_1 : In std_logic;\r
102 PCI_IDSEL : In std_logic;\r
103 REG_OUT_XX7 : In std_logic_vector (7 downto 0);\r
104 TB_DEVSELn : Out std_logic;\r
105 TB_INTAn : Out std_logic;\r
106 TB_PCI_IDSEL : Out std_logic );\r
107 end component;\r
108\r
109 component VEN_REV_ID\r
110 Port ( REV_ID : Out std_logic_vector (7 downto 0);\r
111 VEN_ID : Out std_logic_vector (15 downto 0) );\r
112 end component;\r
113\r
114 component INTERRUPT\r
115 Port ( INT_IN_0 : In std_logic;\r
116 INT_IN_1 : In std_logic;\r
117 INT_IN_2 : In std_logic;\r
118 INT_IN_3 : In std_logic;\r
119 INT_IN_4 : In std_logic;\r
120 INT_IN_5 : In std_logic;\r
121 INT_IN_6 : In std_logic;\r
122 INT_IN_7 : In std_logic;\r
123 INT_MASKE : In std_logic_vector (7 downto 0);\r
124 INT_RES : In std_logic_vector (7 downto 0);\r
125 PCI_CLOCK : In std_logic;\r
126 PCI_RSTn : In std_logic;\r
127 READ_XX5_4 : In std_logic;\r
128 RESET : In std_logic;\r
129 TAST_RESn : In std_logic;\r
130 TAST_SETn : In std_logic;\r
131 TRDYn : In std_logic;\r
132 INT_REG : Out std_logic_vector (7 downto 0);\r
133 INTAn : Out std_logic;\r
134 PCI_INTAn : Out std_logic );\r
135 end component;\r
136\r
137 component FIFO_CONTROL\r
138 Port ( FIFO_RDn : In std_logic;\r
139 FLAG_IN_0 : In std_logic;\r
140 FLAG_IN_4 : In std_logic;\r
141 HOLD : In std_logic;\r
142 KONST_1 : In std_logic;\r
143 PCI_CLOCK : In std_logic;\r
144 PSC_ENABLE : In std_logic;\r
145 R_EFn : In std_logic;\r
146 R_FFn : In std_logic;\r
147 R_HFn : In std_logic;\r
148 RESET : In std_logic;\r
149 S_EFn : In std_logic;\r
150 S_FFn : In std_logic;\r
151 S_FIFO_Q_OUT : In std_logic_vector (7 downto 0);\r
152 S_HFn : In std_logic;\r
153 SERIAL_IN : In std_logic;\r
154 SPC_ENABLE : In std_logic;\r
155 SPC_RDY_IN : In std_logic;\r
156 WRITE_XX1_0 : In std_logic;\r
157 R_ERROR : Out std_logic;\r
158 R_FIFO_D_IN : Out std_logic_vector (7 downto 0);\r
159 R_FIFO_READn : Out std_logic;\r
160 R_FIFO_RESETn : Out std_logic;\r
161 R_FIFO_RETRANSMITn : Out std_logic;\r
162 R_FIFO_WRITEn : Out std_logic;\r
163 RESERVE : Out std_logic;\r
164 S_ERROR : Out std_logic;\r
165 S_FIFO_READn : Out std_logic;\r
166 S_FIFO_RESETn : Out std_logic;\r
167 S_FIFO_RETRANSMITn : Out std_logic;\r
168 S_FIFO_WRITEn : Out std_logic;\r
169 SERIAL_OUT : Out std_logic;\r
170 SPC_RDY_OUT : Out std_logic;\r
171 SR_ERROR : Out std_logic;\r
172 SYNC_FLAG : Out std_logic_vector (7 downto 0) );\r
173 end component;\r
174\r
175 component PCI_TOP\r
176 Port ( FLAG : In std_logic_vector (7 downto 0);\r
177 INT_REG : In std_logic_vector (7 downto 0);\r
178 PCI_CBEn : In std_logic_vector (3 downto 0);\r
179 PCI_CLOCK : In std_logic;\r
180 PCI_FRAMEn : In std_logic;\r
181 PCI_IDSEL : In std_logic;\r
182 PCI_IRDYn : In std_logic;\r
183 PCI_RSTn : In std_logic;\r
184 R_FIFO_Q : In std_logic_vector (7 downto 0);\r
185 REVISON_ID : In std_logic_vector (7 downto 0);\r
186 VENDOR_ID : In std_logic_vector (15 downto 0);\r
187 PCI_AD : InOut std_logic_vector (31 downto 0);\r
188 PCI_PAR : InOut std_logic;\r
189 AD_REG : Out std_logic_vector (31 downto 0);\r
190 DEVSELn : Out std_logic;\r
191 FIFO_RDn : Out std_logic;\r
192 PCI_DEVSELn : Out std_logic;\r
193 PCI_PERRn : Out std_logic;\r
194 PCI_SERRn : Out std_logic;\r
195 PCI_STOPn : Out std_logic;\r
196 PCI_TRDYn : Out std_logic;\r
197 READ_SEL : Out std_logic_vector (1 downto 0);\r
198 READ_XX1_0 : Out std_logic;\r
199 READ_XX3_2 : Out std_logic;\r
200 READ_XX5_4 : Out std_logic;\r
201 READ_XX7_6 : Out std_logic;\r
202 REG_OUT_XX0 : Out std_logic_vector (7 downto 0);\r
203 REG_OUT_XX6 : Out std_logic_vector (7 downto 0);\r
204 REG_OUT_XX7 : Out std_logic_vector (7 downto 0);\r
205 TRDYn : Out std_logic;\r
206 WRITE_XX1_0 : Out std_logic;\r
207 WRITE_XX3_2 : Out std_logic;\r
208 WRITE_XX5_4 : Out std_logic;\r
209 WRITE_XX7_6 : Out std_logic );\r
210 end component;\r
211\r
212component fifo_generator_v3_2\r
213 port (\r
214 clk: IN std_logic;\r
215 din: IN std_logic_VECTOR(7 downto 0);\r
216 rd_en: IN std_logic;\r
217 rst: IN std_logic;\r
218 wr_en: IN std_logic;\r
219 almost_empty: OUT std_logic;\r
220 almost_full: OUT std_logic;\r
221 dout: OUT std_logic_VECTOR(7 downto 0);\r
222 empty: OUT std_logic;\r
223 full: OUT std_logic;\r
224 prog_full: OUT std_logic);\r
225end component;\r
226\r
227component icon\r
228port\r
229 (\r
230 control0 : out std_logic_vector(35 downto 0)\r
231 );\r
232end component;\r
233\r
234 component ila\r
235 port\r
236 (\r
237 control : in std_logic_vector(35 downto 0);\r
238 clk : in std_logic;\r
239 data : in std_logic_vector(95 downto 0);\r
240 trig0 : in std_logic_vector(31 downto 0)\r
241 );\r
242 end component;\r
243\r
244\r
245begin\r
246 SERIAL_IN <= SERIAL_OUT;\r
247 SPC_RDY_IN <= SPC_RDY_OUT;\r
248 LED_2 <= TAST_RESn;\r
249 LED_3 <= TAST_SETn;\r
250 LED_4 <= '0';\r
251 LED_5 <= not watch;\r
252 PCI_INTAn <= watch;\r
253 trig0(31 downto 0) <= (0 => watch, 1 => R_FIFO_READn, 2 => R_FIFO_WRITEn, 3 => S_FIFO_READn, 4 => S_FIFO_WRITEn, others => '0');\r
254 data(0) <= watch;\r
255 \r
256 data(1) <= R_EFn;\r
257 data(2) <= R_HFn;\r
258 data(3) <= R_FFn;\r
259 data(4) <= R_FIFO_READn;\r
260 data(5) <= R_FIFO_RESETn;\r
261 data(6) <= R_FIFO_RTn;\r
262 data(7) <= R_FIFO_WRITEn;\r
263 data(8) <= S_EFn;\r
264 data(9) <= S_HFn;\r
265 data(10) <= S_FFn;\r
266 data(11) <= S_FIFO_READn;\r
267 data(12) <= S_FIFO_RESETn;\r
268 data(13) <= S_FIFO_RTn;\r
269 data(14) <= S_FIFO_WRITEn;\r
270 data(15) <= SERIAL_IN;\r
271 data(16) <= SPC_RDY_IN;\r
272 data(17) <= SERIAL_OUT;\r
273 data(18) <= SPC_RDY_OUT;\r
274 data(26 downto 19) <= S_FIFO_Q_OUT;\r
275 data(34 downto 27) <= R_FIFO_Q_OUT;\r
276 data(66 downto 35) <= PCI_AD(31 downto 0);\r
277 data(70 downto 67) <= PCI_CBEn(3 downto 0);\r
278\r
279 I19 : MESS_1_TB\r
280 Port Map ( DEVSELn=>DEVSELn, INTAn=>INTAn, KONST_1=>KONST_1,\r
281 PCI_IDSEL=>PCI_IDSEL,\r
282 REG_OUT_XX7(7 downto 0)=>REG_OUT_XX7(7 downto 0),\r
283 TB_DEVSELn=>TB_nDEVSEL, TB_INTAn=>TB_nINTA,\r
284 TB_PCI_IDSEL=>TB_IDSEL );\r
285 I18 : VEN_REV_ID\r
286 Port Map ( REV_ID(7 downto 0)=>REVISON_ID(7 downto 0),\r
287 VEN_ID(15 downto 0)=>VENDOR_ID(15 downto 0) );\r
288 I16 : INTERRUPT\r
289 Port Map ( INT_IN_0=>SYNC_FLAG(1), INT_IN_1=>SYNC_FLAG(6),\r
290 INT_IN_2=>KONST_1, INT_IN_3=>KONST_1, INT_IN_4=>KONST_1,\r
291 INT_IN_5=>KONST_1, INT_IN_6=>KONST_1, INT_IN_7=>KONST_1,\r
292 INT_MASKE(7 downto 0)=>REG_OUT_XX6(7 downto 0),\r
293 INT_RES(7 downto 0)=>AD_REG(7 downto 0),\r
294 PCI_CLOCK=>PCI_CLOCK, PCI_RSTn=>PCI_RSTn,\r
295 READ_XX5_4=>READ_XX5_4, RESET=>REG_OUT_XX7(0),\r
296 TAST_RESn=>TAST_RESn, TAST_SETn=>TAST_SETn,\r
297 TRDYn=>TRDYn, INT_REG(7 downto 0)=>INT_REG(7 downto 0),\r
298 INTAn=>INTAn, PCI_INTAn=>watch);\r
299 I14 : FIFO_CONTROL\r
300 Port Map ( FIFO_RDn=>FIFO_RDn, FLAG_IN_0=>R_ERROR,\r
301 FLAG_IN_4=>S_ERROR, HOLD=>READ_SEL(0), KONST_1=>KONST_1,\r
302 PCI_CLOCK=>PCI_CLOCK, PSC_ENABLE=>REG_OUT_XX7(1),\r
303 R_EFn=>R_EFn, R_FFn=>R_FFn, R_HFn=>R_HFn,\r
304 RESET=>REG_OUT_XX7(0), S_EFn=>S_EFn, S_FFn=>S_FFn,\r
305 S_FIFO_Q_OUT(7 downto 0)=>S_FIFO_Q_OUT(7 downto 0),\r
306 S_HFn=>S_HFn, SERIAL_IN=>SERIAL_IN,\r
307 SPC_ENABLE=>REG_OUT_XX7(2), SPC_RDY_IN=>SPC_RDY_IN,\r
308 WRITE_XX1_0=>WRITE_XX1_0, R_ERROR=>R_ERROR,\r
309 R_FIFO_D_IN(7 downto 0)=>R_FIFO_D_IN(7 downto 0),\r
310 R_FIFO_READn=>R_FIFO_READn,\r
311 R_FIFO_RESETn=>R_FIFO_RESETn,\r
312 R_FIFO_RETRANSMITn=>R_FIFO_RTn,\r
313 R_FIFO_WRITEn=>R_FIFO_WRITEn, RESERVE=>RESERVE,\r
314 S_ERROR=>S_ERROR, S_FIFO_READn=>S_FIFO_READn,\r
315 S_FIFO_RESETn=>S_FIFO_RESETn,\r
316 S_FIFO_RETRANSMITn=>S_FIFO_RTn,\r
317 S_FIFO_WRITEn=>S_FIFO_WRITEn, SERIAL_OUT=>SERIAL_OUT,\r
318 SPC_RDY_OUT=>SPC_RDY_OUT, SR_ERROR=>SR_ERROR,\r
319 SYNC_FLAG(7 downto 0)=>SYNC_FLAG(7 downto 0) );\r
320 I1 : PCI_TOP\r
321 Port Map ( FLAG(7 downto 0)=>SYNC_FLAG(7 downto 0),\r
322 INT_REG(7 downto 0)=>INT_REG(7 downto 0),\r
323 PCI_CBEn(3 downto 0)=>PCI_CBEn(3 downto 0),\r
324 PCI_CLOCK=>PCI_CLOCK, PCI_FRAMEn=>PCI_FRAMEn,\r
325 PCI_IDSEL=>PCI_IDSEL, PCI_IRDYn=>PCI_IRDYn,\r
326 PCI_RSTn=>PCI_RSTn,\r
327 R_FIFO_Q(7 downto 0)=>R_FIFO_Q_OUT(7 downto 0),\r
328 REVISON_ID(7 downto 0)=>REVISON_ID(7 downto 0),\r
329 VENDOR_ID(15 downto 0)=>VENDOR_ID(15 downto 0),\r
330 PCI_AD(31 downto 0)=>PCI_AD(31 downto 0),\r
331 PCI_PAR=>PCI_PAR,\r
332 AD_REG(31 downto 0)=>AD_REG(31 downto 0),\r
333 DEVSELn=>DEVSELn, FIFO_RDn=>FIFO_RDn,\r
334 PCI_DEVSELn=>PCI_DEVSELn, PCI_PERRn=>PCI_PERRn,\r
335 PCI_SERRn=>PCI_SERRn, PCI_STOPn=>PCI_STOPn,\r
336 PCI_TRDYn=>PCI_TRDYn,\r
337 READ_SEL(1 downto 0)=>READ_SEL(1 downto 0),\r
338 READ_XX1_0=>READ_XX1_0, READ_XX3_2=>READ_XX3_2,\r
339 READ_XX5_4=>READ_XX5_4, READ_XX7_6=>READ_XX7_6,\r
340 REG_OUT_XX0(7 downto 0)=>S_FIFO_D_IN(7 downto 0),\r
341 REG_OUT_XX6(7 downto 0)=>REG_OUT_XX6(7 downto 0),\r
342 REG_OUT_XX7(7 downto 0)=>REG_OUT_XX7(7 downto 0),\r
343 TRDYn=>TRDYn, WRITE_XX1_0=>WRITE_XX1_0,\r
344 WRITE_XX3_2=>WRITE_XX3_2, WRITE_XX5_4=>WRITE_XX5_4,\r
345 WRITE_XX7_6=>WRITE_XX7_6 );\r
346\r
347receive_fifo : fifo_generator_v3_2\r
348 port map (\r
349 clk => PCI_CLOCK,\r
350 din => R_FIFO_D_IN,\r
351 rd_en => not R_FIFO_READn,\r
352 rst => not R_FIFO_RESETn,\r
353 wr_en => not R_FIFO_WRITEn,\r
354 dout => R_FIFO_Q_OUT,\r
355 empty => R_EFn,\r
356 full => R_FFn,\r
357 prog_full => R_HFn);\r
358\r
359send_fifo : fifo_generator_v3_2\r
360 port map (\r
361 clk => PCI_CLOCK,\r
362 din => S_FIFO_D_IN,\r
363 rd_en => not S_FIFO_READn,\r
364 rst => not S_FIFO_RESETn,\r
365 wr_en => not S_FIFO_WRITEn,\r
366 dout => S_FIFO_Q_OUT,\r
367 empty => S_EFn,\r
368 full => S_FFn,\r
369 prog_full => S_HFn);\r
370\r
371 i_icon : icon\r
372 port map\r
373 (\r
374 control0 => control0\r
375 );\r
376\r
377 i_ila : ila\r
378 port map\r
379 (\r
380 control => control0,\r
381 clk => PCI_CLOCK,\r
382 data => data,\r
383 trig0 => trig0\r
384 );\r
385end SCHEMATIC;\r
Raggedstone-1 projects
Impressum, Datenschutz