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1 | ////////////////////////////////////////////////////////////////////// | |
2 | //// //// | |
3 | //// eth_rxethmac.v //// | |
4 | //// //// | |
5 | //// This file is part of the Ethernet IP core project //// | |
6 | //// http://www.opencores.org/projects/ethmac/ //// | |
7 | //// //// | |
8 | //// Author(s): //// | |
9 | //// - Igor Mohor (igorM@opencores.org) //// | |
10 | //// - Novan Hartadi (novan@vlsi.itb.ac.id) //// | |
11 | //// - Mahmud Galela (mgalela@vlsi.itb.ac.id) //// | |
12 | //// //// | |
13 | //// All additional information is avaliable in the Readme.txt //// | |
14 | //// file. //// | |
15 | //// //// | |
16 | ////////////////////////////////////////////////////////////////////// | |
17 | //// //// | |
18 | //// Copyright (C) 2001 Authors //// | |
19 | //// //// | |
20 | //// This source file may be used and distributed without //// | |
21 | //// restriction provided that this copyright statement is not //// | |
22 | //// removed from the file and that any derivative work contains //// | |
23 | //// the original copyright notice and the associated disclaimer. //// | |
24 | //// //// | |
25 | //// This source file is free software; you can redistribute it //// | |
26 | //// and/or modify it under the terms of the GNU Lesser General //// | |
27 | //// Public License as published by the Free Software Foundation; //// | |
28 | //// either version 2.1 of the License, or (at your option) any //// | |
29 | //// later version. //// | |
30 | //// //// | |
31 | //// This source is distributed in the hope that it will be //// | |
32 | //// useful, but WITHOUT ANY WARRANTY; without even the implied //// | |
33 | //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// | |
34 | //// PURPOSE. See the GNU Lesser General Public License for more //// | |
35 | //// details. //// | |
36 | //// //// | |
37 | //// You should have received a copy of the GNU Lesser General //// | |
38 | //// Public License along with this source; if not, download it //// | |
39 | //// from http://www.opencores.org/lgpl.shtml //// | |
40 | //// //// | |
41 | ////////////////////////////////////////////////////////////////////// | |
42 | // | |
43 | // CVS Revision History | |
44 | // | |
45 | // $Log: eth_rxethmac.v,v $ | |
46 | // Revision 1.1 2007-03-20 17:50:56 sithglan | |
47 | // add shit | |
48 | // | |
49 | // Revision 1.13 2005/02/21 12:48:07 igorm | |
50 | // Warning fixes. | |
51 | // | |
52 | // Revision 1.12 2004/04/26 15:26:23 igorm | |
53 | // - Bug connected to the TX_BD_NUM_Wr signal fixed (bug came in with the | |
54 | // previous update of the core. | |
55 | // - TxBDAddress is set to 0 after the TX is enabled in the MODER register. | |
56 | // - RxBDAddress is set to r_TxBDNum<<1 after the RX is enabled in the MODER | |
57 | // register. (thanks to Mathias and Torbjorn) | |
58 | // - Multicast reception was fixed. Thanks to Ulrich Gries | |
59 | // | |
60 | // Revision 1.11 2004/03/17 09:32:15 igorm | |
61 | // Multicast detection fixed. Only the LSB of the first byte is checked. | |
62 | // | |
63 | // Revision 1.10 2002/11/22 01:57:06 mohor | |
64 | // Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort | |
65 | // synchronized. | |
66 | // | |
67 | // Revision 1.9 2002/11/19 17:35:35 mohor | |
68 | // AddressMiss status is connecting to the Rx BD. AddressMiss is identifying | |
69 | // that a frame was received because of the promiscous mode. | |
70 | // | |
71 | // Revision 1.8 2002/02/16 07:15:27 mohor | |
72 | // Testbench fixed, code simplified, unused signals removed. | |
73 | // | |
74 | // Revision 1.7 2002/02/15 13:44:28 mohor | |
75 | // RxAbort is an output. No need to have is declared as wire. | |
76 | // | |
77 | // Revision 1.6 2002/02/15 11:17:48 mohor | |
78 | // File format changed. | |
79 | // | |
80 | // Revision 1.5 2002/02/14 20:48:43 billditt | |
81 | // Addition of new module eth_addrcheck.v | |
82 | // | |
83 | // Revision 1.4 2002/01/23 10:28:16 mohor | |
84 | // Link in the header changed. | |
85 | // | |
86 | // Revision 1.3 2001/10/19 08:43:51 mohor | |
87 | // eth_timescale.v changed to timescale.v This is done because of the | |
88 | // simulation of the few cores in a one joined project. | |
89 | // | |
90 | // Revision 1.2 2001/09/11 14:17:00 mohor | |
91 | // Few little NCSIM warnings fixed. | |
92 | // | |
93 | // Revision 1.1 2001/08/06 14:44:29 mohor | |
94 | // A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex). | |
95 | // Include files fixed to contain no path. | |
96 | // File names and module names changed ta have a eth_ prologue in the name. | |
97 | // File eth_timescale.v is used to define timescale | |
98 | // All pin names on the top module are changed to contain _I, _O or _OE at the end. | |
99 | // Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O | |
100 | // and Mdo_OE. The bidirectional signal must be created on the top level. This | |
101 | // is done due to the ASIC tools. | |
102 | // | |
103 | // Revision 1.1 2001/07/30 21:23:42 mohor | |
104 | // Directory structure changed. Files checked and joind together. | |
105 | // | |
106 | // Revision 1.1 2001/06/27 21:26:19 mohor | |
107 | // Initial release of the RxEthMAC module. | |
108 | // | |
109 | // | |
110 | // | |
111 | // | |
112 | // | |
113 | ||
114 | `include "timescale.v" | |
115 | ||
116 | ||
117 | module eth_rxethmac (MRxClk, MRxDV, MRxD, Reset, Transmitting, MaxFL, r_IFG, HugEn, DlyCrcEn, | |
118 | RxData, RxValid, RxStartFrm, RxEndFrm, ByteCnt, ByteCntEq0, ByteCntGreat2, | |
119 | ByteCntMaxFrame, CrcError, StateIdle, StatePreamble, StateSFD, StateData, | |
120 | MAC, r_Pro, r_Bro,r_HASH0, r_HASH1, RxAbort, AddressMiss, PassAll, ControlFrmAddressOK | |
121 | ); | |
122 | ||
123 | parameter Tp = 1; | |
124 | ||
125 | ||
126 | ||
127 | input MRxClk; | |
128 | input MRxDV; | |
129 | input [3:0] MRxD; | |
130 | input Transmitting; | |
131 | input HugEn; | |
132 | input DlyCrcEn; | |
133 | input [15:0] MaxFL; | |
134 | input r_IFG; | |
135 | input Reset; | |
136 | input [47:0] MAC; // Station Address | |
137 | input r_Bro; // broadcast disable | |
138 | input r_Pro; // promiscuous enable | |
139 | input [31:0] r_HASH0; // lower 4 bytes Hash Table | |
140 | input [31:0] r_HASH1; // upper 4 bytes Hash Table | |
141 | input PassAll; | |
142 | input ControlFrmAddressOK; | |
143 | ||
144 | output [7:0] RxData; | |
145 | output RxValid; | |
146 | output RxStartFrm; | |
147 | output RxEndFrm; | |
148 | output [15:0] ByteCnt; | |
149 | output ByteCntEq0; | |
150 | output ByteCntGreat2; | |
151 | output ByteCntMaxFrame; | |
152 | output CrcError; | |
153 | output StateIdle; | |
154 | output StatePreamble; | |
155 | output StateSFD; | |
156 | output [1:0] StateData; | |
157 | output RxAbort; | |
158 | output AddressMiss; | |
159 | ||
160 | reg [7:0] RxData; | |
161 | reg RxValid; | |
162 | reg RxStartFrm; | |
163 | reg RxEndFrm; | |
164 | reg Broadcast; | |
165 | reg Multicast; | |
166 | reg [5:0] CrcHash; | |
167 | reg CrcHashGood; | |
168 | reg DelayData; | |
169 | reg [7:0] LatchedByte; | |
170 | reg [7:0] RxData_d; | |
171 | reg RxValid_d; | |
172 | reg RxStartFrm_d; | |
173 | reg RxEndFrm_d; | |
174 | ||
175 | wire MRxDEqD; | |
176 | wire MRxDEq5; | |
177 | wire StateDrop; | |
178 | wire ByteCntEq1; | |
179 | wire ByteCntEq2; | |
180 | wire ByteCntEq3; | |
181 | wire ByteCntEq4; | |
182 | wire ByteCntEq5; | |
183 | wire ByteCntEq6; | |
184 | wire ByteCntEq7; | |
185 | wire ByteCntSmall7; | |
186 | wire [31:0] Crc; | |
187 | wire Enable_Crc; | |
188 | wire Initialize_Crc; | |
189 | wire [3:0] Data_Crc; | |
190 | wire GenerateRxValid; | |
191 | wire GenerateRxStartFrm; | |
192 | wire GenerateRxEndFrm; | |
193 | wire DribbleRxEndFrm; | |
194 | wire [3:0] DlyCrcCnt; | |
195 | wire IFGCounterEq24; | |
196 | ||
197 | assign MRxDEqD = MRxD == 4'hd; | |
198 | assign MRxDEq5 = MRxD == 4'h5; | |
199 | ||
200 | ||
201 | // Rx State Machine module | |
202 | eth_rxstatem rxstatem1 (.MRxClk(MRxClk), .Reset(Reset), .MRxDV(MRxDV), .ByteCntEq0(ByteCntEq0), | |
203 | .ByteCntGreat2(ByteCntGreat2), .Transmitting(Transmitting), .MRxDEq5(MRxDEq5), | |
204 | .MRxDEqD(MRxDEqD), .IFGCounterEq24(IFGCounterEq24), .ByteCntMaxFrame(ByteCntMaxFrame), | |
205 | .StateData(StateData), .StateIdle(StateIdle), .StatePreamble(StatePreamble), | |
206 | .StateSFD(StateSFD), .StateDrop(StateDrop) | |
207 | ); | |
208 | ||
209 | ||
210 | // Rx Counters module | |
211 | eth_rxcounters rxcounters1 (.MRxClk(MRxClk), .Reset(Reset), .MRxDV(MRxDV), .StateIdle(StateIdle), | |
212 | .StateSFD(StateSFD), .StateData(StateData), .StateDrop(StateDrop), | |
213 | .StatePreamble(StatePreamble), .MRxDEqD(MRxDEqD), .DlyCrcEn(DlyCrcEn), | |
214 | .DlyCrcCnt(DlyCrcCnt), .Transmitting(Transmitting), .MaxFL(MaxFL), .r_IFG(r_IFG), | |
215 | .HugEn(HugEn), .IFGCounterEq24(IFGCounterEq24), .ByteCntEq0(ByteCntEq0), | |
216 | .ByteCntEq1(ByteCntEq1), .ByteCntEq2(ByteCntEq2), .ByteCntEq3(ByteCntEq3), | |
217 | .ByteCntEq4(ByteCntEq4), .ByteCntEq5(ByteCntEq5), .ByteCntEq6(ByteCntEq6), | |
218 | .ByteCntEq7(ByteCntEq7), .ByteCntGreat2(ByteCntGreat2), | |
219 | .ByteCntSmall7(ByteCntSmall7), .ByteCntMaxFrame(ByteCntMaxFrame), | |
220 | .ByteCntOut(ByteCnt) | |
221 | ); | |
222 | ||
223 | // Rx Address Check | |
224 | ||
225 | eth_rxaddrcheck rxaddrcheck1 | |
226 | (.MRxClk(MRxClk), .Reset( Reset), .RxData(RxData), | |
227 | .Broadcast (Broadcast), .r_Bro (r_Bro), .r_Pro(r_Pro), | |
228 | .ByteCntEq6(ByteCntEq6), .ByteCntEq7(ByteCntEq7), .ByteCntEq2(ByteCntEq2), | |
229 | .ByteCntEq3(ByteCntEq3), .ByteCntEq4(ByteCntEq4), .ByteCntEq5(ByteCntEq5), | |
230 | .HASH0(r_HASH0), .HASH1(r_HASH1), | |
231 | .CrcHash(CrcHash), .CrcHashGood(CrcHashGood), .StateData(StateData), | |
232 | .Multicast(Multicast), .MAC(MAC), .RxAbort(RxAbort), | |
233 | .RxEndFrm(RxEndFrm), .AddressMiss(AddressMiss), .PassAll(PassAll), | |
234 | .ControlFrmAddressOK(ControlFrmAddressOK) | |
235 | ); | |
236 | ||
237 | ||
238 | assign Enable_Crc = MRxDV & (|StateData & ~ByteCntMaxFrame); | |
239 | assign Initialize_Crc = StateSFD | DlyCrcEn & (|DlyCrcCnt[3:0]) & DlyCrcCnt[3:0] < 4'h9; | |
240 | ||
241 | assign Data_Crc[0] = MRxD[3]; | |
242 | assign Data_Crc[1] = MRxD[2]; | |
243 | assign Data_Crc[2] = MRxD[1]; | |
244 | assign Data_Crc[3] = MRxD[0]; | |
245 | ||
246 | ||
247 | // Connecting module Crc | |
248 | eth_crc crcrx (.Clk(MRxClk), .Reset(Reset), .Data(Data_Crc), .Enable(Enable_Crc), .Initialize(Initialize_Crc), | |
249 | .Crc(Crc), .CrcError(CrcError) | |
250 | ); | |
251 | ||
252 | ||
253 | ||
254 | // Latching CRC for use in the hash table | |
255 | ||
256 | always @ (posedge MRxClk) | |
257 | begin | |
258 | CrcHashGood <= #Tp StateData[0] & ByteCntEq6; | |
259 | end | |
260 | ||
261 | always @ (posedge MRxClk) | |
262 | begin | |
263 | if(Reset | StateIdle) | |
264 | CrcHash[5:0] <= #Tp 6'h0; | |
265 | else | |
266 | if(StateData[0] & ByteCntEq6) | |
267 | CrcHash[5:0] <= #Tp Crc[31:26]; | |
268 | end | |
269 | ||
270 | ||
271 | // Output byte stream | |
272 | always @ (posedge MRxClk or posedge Reset) | |
273 | begin | |
274 | if(Reset) | |
275 | begin | |
276 | RxData_d[7:0] <= #Tp 8'h0; | |
277 | DelayData <= #Tp 1'b0; | |
278 | LatchedByte[7:0] <= #Tp 8'h0; | |
279 | RxData[7:0] <= #Tp 8'h0; | |
280 | end | |
281 | else | |
282 | begin | |
283 | LatchedByte[7:0] <= #Tp {MRxD[3:0], LatchedByte[7:4]}; // Latched byte | |
284 | DelayData <= #Tp StateData[0]; | |
285 | ||
286 | if(GenerateRxValid) | |
287 | RxData_d[7:0] <= #Tp LatchedByte[7:0] & {8{|StateData}}; // Data goes through only in data state | |
288 | else | |
289 | if(~DelayData) | |
290 | RxData_d[7:0] <= #Tp 8'h0; // Delaying data to be valid for two cycles. Zero when not active. | |
291 | ||
292 | RxData[7:0] <= #Tp RxData_d[7:0]; // Output data byte | |
293 | end | |
294 | end | |
295 | ||
296 | ||
297 | ||
298 | always @ (posedge MRxClk or posedge Reset) | |
299 | begin | |
300 | if(Reset) | |
301 | Broadcast <= #Tp 1'b0; | |
302 | else | |
303 | begin | |
304 | if(StateData[0] & ~(&LatchedByte[7:0]) & ByteCntSmall7) | |
305 | Broadcast <= #Tp 1'b0; | |
306 | else | |
307 | if(StateData[0] & (&LatchedByte[7:0]) & ByteCntEq1) | |
308 | Broadcast <= #Tp 1'b1; | |
309 | else | |
310 | if(RxAbort | RxEndFrm) | |
311 | Broadcast <= #Tp 1'b0; | |
312 | end | |
313 | end | |
314 | ||
315 | ||
316 | always @ (posedge MRxClk or posedge Reset) | |
317 | begin | |
318 | if(Reset) | |
319 | Multicast <= #Tp 1'b0; | |
320 | else | |
321 | begin | |
322 | if(StateData[0] & ByteCntEq1 & LatchedByte[0]) | |
323 | Multicast <= #Tp 1'b1; | |
324 | else if(RxAbort | RxEndFrm) | |
325 | Multicast <= #Tp 1'b0; | |
326 | end | |
327 | end | |
328 | ||
329 | ||
330 | assign GenerateRxValid = StateData[0] & (~ByteCntEq0 | DlyCrcCnt >= 4'h3); | |
331 | ||
332 | always @ (posedge MRxClk or posedge Reset) | |
333 | begin | |
334 | if(Reset) | |
335 | begin | |
336 | RxValid_d <= #Tp 1'b0; | |
337 | RxValid <= #Tp 1'b0; | |
338 | end | |
339 | else | |
340 | begin | |
341 | RxValid_d <= #Tp GenerateRxValid; | |
342 | RxValid <= #Tp RxValid_d; | |
343 | end | |
344 | end | |
345 | ||
346 | ||
347 | assign GenerateRxStartFrm = StateData[0] & (ByteCntEq1 & ~DlyCrcEn | DlyCrcCnt == 4'h3 & DlyCrcEn); | |
348 | ||
349 | always @ (posedge MRxClk or posedge Reset) | |
350 | begin | |
351 | if(Reset) | |
352 | begin | |
353 | RxStartFrm_d <= #Tp 1'b0; | |
354 | RxStartFrm <= #Tp 1'b0; | |
355 | end | |
356 | else | |
357 | begin | |
358 | RxStartFrm_d <= #Tp GenerateRxStartFrm; | |
359 | RxStartFrm <= #Tp RxStartFrm_d; | |
360 | end | |
361 | end | |
362 | ||
363 | ||
364 | assign GenerateRxEndFrm = StateData[0] & (~MRxDV & ByteCntGreat2 | ByteCntMaxFrame); | |
365 | assign DribbleRxEndFrm = StateData[1] & ~MRxDV & ByteCntGreat2; | |
366 | ||
367 | ||
368 | always @ (posedge MRxClk or posedge Reset) | |
369 | begin | |
370 | if(Reset) | |
371 | begin | |
372 | RxEndFrm_d <= #Tp 1'b0; | |
373 | RxEndFrm <= #Tp 1'b0; | |
374 | end | |
375 | else | |
376 | begin | |
377 | RxEndFrm_d <= #Tp GenerateRxEndFrm; | |
378 | RxEndFrm <= #Tp RxEndFrm_d | DribbleRxEndFrm; | |
379 | end | |
380 | end | |
381 | ||
382 | ||
383 | endmodule |