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[raggedstone] / heartbeat / source / top_raggedstone.vhd
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1--+-------------------------------------------------------------------------------------------------+\r
2--| |\r
3--| File: top.vhd |\r
4--| |\r
5--| Components: pci32lite.vhd |\r
6--| pciwbsequ.vhd |\r
7--| pcidmux.vhd |\r
8--| pciregs.vhd |\r
9--| pcipargen.vhd |\r
10--| -- Libs -- |\r
11--| ona.vhd |\r
12--| |\r
13--| Description: RS1 PCI Demo : (TOP) Main file. |\r
14--| |\r
15--| |\r
16--| |\r
17--+-------------------------------------------------------------------------------------------------+\r
18--| |\r
19--| Revision history : |\r
20--| Date Version Author Description |\r
21--| |\r
22--| |\r
23--| To do: |\r
24--| |\r
25--+-------------------------------------------------------------------------------------------------+\r
26\r
27\r
28--+-----------------------------------------------------------------------------+\r
29--| LIBRARIES |\r
30--+-----------------------------------------------------------------------------+\r
31\r
32library ieee;\r
33use ieee.std_logic_1164.all;\r
34use ieee.std_logic_arith.all;\r
35use ieee.std_logic_unsigned.all;\r
36\r
37--+-----------------------------------------------------------------------------+\r
38--| ENTITY |\r
39--+-----------------------------------------------------------------------------+\r
40\r
41entity pci_7seg is\r
42port (\r
43\r
44 -- General \r
45 PCI_CLK : in std_logic;\r
46 PCI_nRES : in std_logic;\r
47 \r
48 -- PCI target 32bits\r
49 PCI_AD : inout std_logic_vector(31 downto 0);\r
50 PCI_CBE : in std_logic_vector(3 downto 0);\r
51 PCI_PAR : out std_logic; \r
52 PCI_nFRAME : in std_logic;\r
53 PCI_nIRDY : in std_logic;\r
54 PCI_nTRDY : out std_logic;\r
55 PCI_nDEVSEL : out std_logic;\r
56 PCI_nSTOP : out std_logic;\r
57 PCI_IDSEL : in std_logic;\r
58 PCI_nPERR : out std_logic;\r
59 PCI_nSERR : out std_logic;\r
60 PCI_nINT : out std_logic;\r
61 \r
62 -- 7seg\r
63 DISP_SEL : inout std_logic_vector(3 downto 0);\r
64 DISP_LED : out std_logic_vector(6 downto 0);\r
65 \r
66 -- debug signals\r
67 LED_INIT : out std_logic;\r
68 LED_ACCESS : out std_logic;\r
69 LED_ALIVE : out std_logic;\r
70\r
71 -- vga signals\r
72 hs : out std_logic;\r
73 vs : out std_logic;\r
74 red, grn, blu : out std_logic;\r
75 mclk : in std_logic\r
76\r
77);\r
78end pci_7seg;\r
79\r
80\r
81--+-----------------------------------------------------------------------------+\r
82--| ARCHITECTURE |\r
83--+-----------------------------------------------------------------------------+\r
84\r
85architecture pci_7seg_arch of pci_7seg is\r
86\r
87\r
88--+-----------------------------------------------------------------------------+\r
89--| COMPONENTS |\r
90--+-----------------------------------------------------------------------------+\r
91\r
92component pci32tlite\r
93port (\r
94\r
95 -- General \r
96 clk33 : in std_logic;\r
97 nrst : in std_logic;\r
98 \r
99 -- PCI target 32bits\r
100 ad : inout std_logic_vector(31 downto 0);\r
101 cbe : in std_logic_vector(3 downto 0);\r
102 par : out std_logic; \r
103 frame : in std_logic;\r
104 irdy : in std_logic;\r
105 trdy : out std_logic;\r
106 devsel : out std_logic;\r
107 stop : out std_logic;\r
108 idsel : in std_logic;\r
109 perr : out std_logic;\r
110 serr : out std_logic;\r
111 intb : out std_logic;\r
112 \r
113 -- Master whisbone\r
114 wb_adr_o : out std_logic_vector(24 downto 1); \r
115 wb_dat_i : in std_logic_vector(15 downto 0);\r
116 wb_dat_o : out std_logic_vector(15 downto 0);\r
117 wb_sel_o : out std_logic_vector(1 downto 0);\r
118 wb_we_o : out std_logic;\r
119 wb_stb_o : out std_logic;\r
120 wb_cyc_o : out std_logic;\r
121 wb_ack_i : in std_logic;\r
122 wb_err_i : in std_logic;\r
123 wb_int_i : in std_logic;\r
124\r
125 -- debug signals\r
126 debug_init : out std_logic;\r
127 debug_access : out std_logic \r
128\r
129 );\r
130end component;\r
131\r
132\r
133component wb_7seg_new\r
134port (\r
135 \r
136 -- General \r
137 clk_i : in std_logic;\r
138 nrst_i : in std_logic;\r
139 \r
140 -- Master whisbone\r
141 wb_adr_i : in std_logic_vector(24 downto 1); \r
142 wb_dat_o : out std_logic_vector(15 downto 0);\r
143 wb_dat_i : in std_logic_vector(15 downto 0);\r
144 wb_sel_i : in std_logic_vector(1 downto 0);\r
145 wb_we_i : in std_logic;\r
146 wb_stb_i : in std_logic;\r
147 wb_cyc_i : in std_logic;\r
148 wb_ack_o : out std_logic;\r
149 wb_err_o : out std_logic;\r
150 wb_int_o : out std_logic;\r
151\r
152 -- 7seg\r
153 DISP_SEL : inout std_logic_vector(3 downto 0);\r
154 DISP_LED : out std_logic_vector(6 downto 0)\r
155\r
156 );\r
157end component;\r
158\r
159\r
160component vgaController is\r
161 Port ( mclk : in std_logic;\r
162 hs : out std_logic;\r
163 vs : out std_logic;\r
164 red : out std_logic;\r
165 grn : out std_logic;\r
166 blu : out std_logic);\r
167end component;\r
168\r
169\r
170--+-----------------------------------------------------------------------------+\r
171--| CONSTANTS |\r
172--+-----------------------------------------------------------------------------+\r
173--+-----------------------------------------------------------------------------+\r
174--| SIGNALS |\r
175--+-----------------------------------------------------------------------------+\r
176\r
177 signal wb_adr : std_logic_vector(24 downto 1); \r
178 signal wb_dat_out : std_logic_vector(15 downto 0);\r
179 signal wb_dat_in : std_logic_vector(15 downto 0);\r
180 signal wb_sel : std_logic_vector(1 downto 0);\r
181 signal wb_we : std_logic;\r
182 signal wb_stb : std_logic;\r
183 signal wb_cyc : std_logic;\r
184 signal wb_ack : std_logic;\r
185 signal wb_err : std_logic;\r
186 signal wb_int : std_logic;\r
187\r
188\r
189begin\r
190\r
191 LED_ALIVE <= '1';\r
192--+-------------------------------------------------------------------------+\r
193--| Component instances |\r
194--+-------------------------------------------------------------------------+\r
195\r
196 vga1: vgaController port map (mclk => mclk,\r
197 hs => hs,\r
198 vs => vs,\r
199 red => red,\r
200 grn => grn,\r
201 blu => blu);\r
202\r
203--+-----------------------------------------+\r
204--| PCI Target |\r
205--+-----------------------------------------+\r
206\r
207u_pci: component pci32tlite\r
208port map(\r
209 clk33 => PCI_CLK,\r
210 nrst => PCI_nRES,\r
211 ad => PCI_AD,\r
212 cbe => PCI_CBE,\r
213 par => PCI_PAR,\r
214 frame => PCI_nFRAME,\r
215 irdy => PCI_nIRDY,\r
216 trdy => PCI_nTRDY,\r
217 devsel => PCI_nDEVSEL,\r
218 stop => PCI_nSTOP,\r
219 idsel => PCI_IDSEL,\r
220 perr => PCI_nPERR,\r
221 serr => PCI_nSERR,\r
222 intb => PCI_nINT,\r
223 wb_adr_o => wb_adr, \r
224 wb_dat_i => wb_dat_out,\r
225 wb_dat_o => wb_dat_in,\r
226 wb_sel_o => wb_sel, \r
227 wb_we_o => wb_we,\r
228 wb_stb_o => wb_stb, \r
229 wb_cyc_o => wb_cyc,\r
230 wb_ack_i => wb_ack,\r
231 wb_err_i => wb_err,\r
232 wb_int_i => wb_int,\r
233 debug_init => LED_INIT,\r
234 debug_access => LED_ACCESS\r
235 );\r
236\r
237--+-----------------------------------------+\r
238--| WB-7seg |\r
239--+-----------------------------------------+\r
240\r
241u_wb: component wb_7seg_new\r
242port map(\r
243 clk_i => PCI_CLK,\r
244 nrst_i => PCI_nRES,\r
245 wb_adr_i => wb_adr, \r
246 wb_dat_o => wb_dat_out,\r
247 wb_dat_i => wb_dat_in,\r
248 wb_sel_i => wb_sel,\r
249 wb_we_i => wb_we,\r
250 wb_stb_i => wb_stb,\r
251 wb_cyc_i => wb_cyc,\r
252 wb_ack_o => wb_ack,\r
253 wb_err_o => wb_err,\r
254 wb_int_o => wb_int,\r
255 DISP_SEL => DISP_SEL,\r
256 DISP_LED => DISP_LED\r
257);\r
258\r
259end pci_7seg_arch;\r
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