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Commit	Line	Data
	1	//////////////////////////////////////////////////////////////////////
	2	//// ////
	3	//// File name: pci_in_reg.v ////
	4	//// ////
	5	//// This file is part of the "PCI bridge" project ////
	6	//// http://www.opencores.org/cores/pci/ ////
	7	//// ////
	8	//// Author(s): ////
	9	//// - Tadej Markovic, tadej@opencores.org ////
	10	//// ////
	11	//// All additional information is avaliable in the README.txt ////
	12	//// file. ////
	13	//// ////
	14	//// ////
	15	//////////////////////////////////////////////////////////////////////
	16	//// ////
	17	//// Copyright (C) 2000 Tadej Markovic, tadej@opencores.org ////
	18	//// ////
	19	//// This source file may be used and distributed without ////
	20	//// restriction provided that this copyright statement is not ////
	21	//// removed from the file and that any derivative work contains ////
	22	//// the original copyright notice and the associated disclaimer. ////
	23	//// ////
	24	//// This source file is free software; you can redistribute it ////
	25	//// and/or modify it under the terms of the GNU Lesser General ////
	26	//// Public License as published by the Free Software Foundation; ////
	27	//// either version 2.1 of the License, or (at your option) any ////
	28	//// later version. ////
	29	//// ////
	30	//// This source is distributed in the hope that it will be ////
	31	//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
	32	//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
	33	//// PURPOSE. See the GNU Lesser General Public License for more ////
	34	//// details. ////
	35	//// ////
	36	//// You should have received a copy of the GNU Lesser General ////
	37	//// Public License along with this source; if not, download it ////
	38	//// from http://www.opencores.org/lgpl.shtml ////
	39	//// ////
	40	//////////////////////////////////////////////////////////////////////
	41	//
	42	// CVS Revision History
	43	//
	44	// $Log: pci_in_reg.v,v $
	45	// Revision 1.1 2007-03-20 17:50:56 sithglan
	46	// add shit
	47	//
	48	// Revision 1.5 2003/12/19 11:11:30 mihad
	49	// Compact PCI Hot Swap support added.
	50	// New testcases added.
	51	// Specification updated.
	52	// Test application changed to support WB B3 cycles.
	53	//
	54	// Revision 1.4 2003/01/27 16:49:31 mihad
	55	// Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed.
	56	//
	57	// Revision 1.3 2002/02/01 15:25:12 mihad
	58	// Repaired a few bugs, updated specification, added test bench files and design document
	59	//
	60	// Revision 1.2 2001/10/05 08:14:29 mihad
	61	// Updated all files with inclusion of timescale file for simulation purposes.
	62	//
	63	// Revision 1.1.1.1 2001/10/02 15:33:46 mihad
	64	// New project directory structure
	65	//
	66	//
	67
	68	// synopsys translate_off
	69	`include "timescale.v"
	70	// synopsys translate_on
	71	`include "pci_constants.v"
	72	// Module is used for registering PCI input signals
	73	// It provides data flip flops with reset
	74	module pci_in_reg
	75	(
	76	reset_in,
	77	clk_in,
	78	init_complete_in,
	79
	80	pci_gnt_in,
	81	pci_frame_in,
	82	pci_irdy_in,
	83	pci_trdy_in,
	84	pci_stop_in,
	85	pci_devsel_in,
	86	pci_idsel_in,
	87	pci_ad_in,
	88	pci_cbe_in,
	89
	90	pci_gnt_reg_out,
	91	pci_frame_reg_out,
	92	pci_irdy_reg_out,
	93	pci_trdy_reg_out,
	94	pci_stop_reg_out,
	95	pci_devsel_reg_out,
	96	pci_idsel_reg_out,
	97	pci_ad_reg_out,
	98	pci_cbe_reg_out
	99
	100	);
	101
	102	input reset_in, clk_in, init_complete_in ;
	103
	104	input pci_gnt_in ;
	105	input pci_frame_in ;
	106	input pci_irdy_in ;
	107	input pci_trdy_in ;
	108	input pci_stop_in ;
	109	input pci_devsel_in ;
	110	input pci_idsel_in ;
	111	input [31:0] pci_ad_in ;
	112	input [3:0] pci_cbe_in ;
	113
	114	output pci_gnt_reg_out ;
	115	output pci_frame_reg_out ;
	116	output pci_irdy_reg_out ;
	117	output pci_trdy_reg_out ;
	118	output pci_stop_reg_out ;
	119	output pci_devsel_reg_out ;
	120	output pci_idsel_reg_out ;
	121	output [31:0] pci_ad_reg_out ;
	122	output [3:0] pci_cbe_reg_out ;
	123
	124
	125	reg pci_gnt_reg_out ;
	126	reg pci_frame_reg_out ;
	127	reg pci_irdy_reg_out ;
	128	reg pci_trdy_reg_out ;
	129	reg pci_stop_reg_out ;
	130	reg pci_devsel_reg_out ;
	131	reg pci_idsel_reg_out ;
	132	reg [31:0] pci_ad_reg_out ;
	133	reg [3:0] pci_cbe_reg_out ;
	134
	135	always@(posedge reset_in or posedge clk_in)
	136	begin
	137	if ( reset_in )
	138	begin
	139	pci_gnt_reg_out <= #`FF_DELAY 1'b1 ;
	140	pci_frame_reg_out <= #`FF_DELAY 1'b0 ;
	141	pci_irdy_reg_out <= #`FF_DELAY 1'b1 ;
	142	pci_trdy_reg_out <= #`FF_DELAY 1'b1 ;
	143	pci_stop_reg_out <= #`FF_DELAY 1'b1 ;
	144	pci_devsel_reg_out <= #`FF_DELAY 1'b1 ;
	145	pci_idsel_reg_out <= #`FF_DELAY 1'b0 ; // active high!
	146	pci_ad_reg_out <= #`FF_DELAY 32'h0000_0000 ;
	147	pci_cbe_reg_out <= #`FF_DELAY 4'h0 ;
	148	end
	149	else if (init_complete_in)
	150	begin
	151	pci_gnt_reg_out <= #`FF_DELAY pci_gnt_in ;
	152	pci_frame_reg_out <= #`FF_DELAY pci_frame_in ;
	153	pci_irdy_reg_out <= #`FF_DELAY pci_irdy_in ;
	154	pci_trdy_reg_out <= #`FF_DELAY pci_trdy_in ;
	155	pci_stop_reg_out <= #`FF_DELAY pci_stop_in ;
	156	pci_devsel_reg_out <= #`FF_DELAY pci_devsel_in ;
	157	pci_idsel_reg_out <= #`FF_DELAY pci_idsel_in ;
	158	pci_ad_reg_out <= #`FF_DELAY pci_ad_in ;
	159	pci_cbe_reg_out <= #`FF_DELAY pci_cbe_in ;
	160	end
	161	end
	162
	163	endmodule