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1-- VHDL model created from schematic top.sch -- Jan 09 20:54:18 2007\r
2\r
3\r
4\r
5LIBRARY ieee;\r
6\r
7USE ieee.std_logic_1164.ALL;\r
8USE ieee.numeric_std.ALL;\r
9\r
10\r
11entity dhwk is\r
12 Port ( KONST_1 : In std_logic;\r
13 PCI_CBEn : In std_logic_vector (3 downto 0);\r
14 PCI_CLOCK : In std_logic;\r
15 PCI_FRAMEn : In std_logic;\r
16 PCI_IDSEL : In std_logic;\r
17 PCI_IRDYn : In std_logic;\r
18 PCI_RSTn : In std_logic;\r
19-- SERIAL_IN : In std_logic;\r
20-- SPC_RDY_IN : In std_logic;\r
21 TAST_RESn : In std_logic;\r
22 TAST_SETn : In std_logic;\r
23 LED_2 : out std_logic;\r
24 LED_3 : out std_logic;\r
25 LED_4 : out std_logic;\r
26 LED_5 : out std_logic;\r
27 PCI_AD : InOut std_logic_vector (31 downto 0);\r
28 PCI_PAR : InOut std_logic;\r
29 PCI_DEVSELn : Out std_logic;\r
30 PCI_INTAn : Out std_logic;\r
31 PCI_PERRn : Out std_logic;\r
32 PCI_SERRn : Out std_logic;\r
33 PCI_STOPn : Out std_logic;\r
34 PCI_TRDYn : Out std_logic;\r
35-- SERIAL_OUT : Out std_logic;\r
36-- SPC_RDY_OUT : Out std_logic;\r
37 TB_IDSEL : Out std_logic;\r
38 TB_nDEVSEL : Out std_logic;\r
39 TB_nINTA : Out std_logic );\r
40end dhwk;\r
41\r
42architecture SCHEMATIC of dhwk is\r
43\r
44 SIGNAL gnd : std_logic := '0';\r
45 SIGNAL vcc : std_logic := '1';\r
46\r
47 signal READ_XX7_6 : std_logic;\r
48 signal RESERVE : std_logic;\r
49 signal SR_ERROR : std_logic;\r
50 signal R_ERROR : std_logic;\r
51 signal S_ERROR : std_logic;\r
52 signal WRITE_XX3_2 : std_logic;\r
53 signal WRITE_XX5_4 : std_logic;\r
54 signal WRITE_XX7_6 : std_logic;\r
55 signal READ_XX1_0 : std_logic;\r
56 signal READ_XX3_2 : std_logic;\r
57 signal INTAn : std_logic;\r
58 signal TRDYn : std_logic;\r
59 signal READ_XX5_4 : std_logic;\r
60 signal DEVSELn : std_logic;\r
61 signal FIFO_RDn : std_logic;\r
62 signal WRITE_XX1_0 : std_logic;\r
63 signal REG_OUT_XX6 : std_logic_vector (7 downto 0);\r
64 signal SYNC_FLAG : std_logic_vector (7 downto 0);\r
65 signal INT_REG : std_logic_vector (7 downto 0);\r
66 signal REVISON_ID : std_logic_vector (7 downto 0);\r
67 signal VENDOR_ID : std_logic_vector (15 downto 0);\r
68 signal READ_SEL : std_logic_vector (1 downto 0);\r
69 signal AD_REG : std_logic_vector (31 downto 0);\r
70 signal REG_OUT_XX7 : std_logic_vector (7 downto 0);\r
71 signal R_EFn : std_logic;\r
72 signal R_FFn : std_logic;\r
73 signal R_FIFO_Q_OUT : std_logic_vector (7 downto 0);\r
74 signal R_HFn : std_logic;\r
75 signal S_EFn : std_logic;\r
76 signal S_FFn : std_logic;\r
77 signal S_FIFO_Q_OUT : std_logic_vector (7 downto 0);\r
78 signal S_HFn : std_logic;\r
79 signal R_FIFO_D_IN : std_logic_vector (7 downto 0);\r
80 signal R_FIFO_READn : std_logic;\r
81 signal R_FIFO_RESETn : std_logic;\r
82 signal R_FIFO_RTn : std_logic;\r
83 signal R_FIFO_WRITEn : std_logic;\r
84 signal S_FIFO_D_IN : std_logic_vector (7 downto 0);\r
85 signal S_FIFO_READn : std_logic;\r
86 signal S_FIFO_RESETn : std_logic;\r
87 signal S_FIFO_RTn : std_logic;\r
88 signal S_FIFO_WRITEn : std_logic;\r
89 signal SERIAL_IN : std_logic;\r
90 signal SPC_RDY_IN : std_logic;\r
91 signal SERIAL_OUT : std_logic;\r
92 signal SPC_RDY_OUT : std_logic;\r
93 signal watch : std_logic;\r
94\r
95 component MESS_1_TB\r
96 Port ( DEVSELn : In std_logic;\r
97 INTAn : In std_logic;\r
98 KONST_1 : In std_logic;\r
99 PCI_IDSEL : In std_logic;\r
100 REG_OUT_XX7 : In std_logic_vector (7 downto 0);\r
101 TB_DEVSELn : Out std_logic;\r
102 TB_INTAn : Out std_logic;\r
103 TB_PCI_IDSEL : Out std_logic );\r
104 end component;\r
105\r
106 component VEN_REV_ID\r
107 Port ( REV_ID : Out std_logic_vector (7 downto 0);\r
108 VEN_ID : Out std_logic_vector (15 downto 0) );\r
109 end component;\r
110\r
111 component INTERRUPT\r
112 Port ( INT_IN_0 : In std_logic;\r
113 INT_IN_1 : In std_logic;\r
114 INT_IN_2 : In std_logic;\r
115 INT_IN_3 : In std_logic;\r
116 INT_IN_4 : In std_logic;\r
117 INT_IN_5 : In std_logic;\r
118 INT_IN_6 : In std_logic;\r
119 INT_IN_7 : In std_logic;\r
120 INT_MASKE : In std_logic_vector (7 downto 0);\r
121 INT_RES : In std_logic_vector (7 downto 0);\r
122 PCI_CLOCK : In std_logic;\r
123 PCI_RSTn : In std_logic;\r
124 READ_XX5_4 : In std_logic;\r
125 RESET : In std_logic;\r
126 TAST_RESn : In std_logic;\r
127 TAST_SETn : In std_logic;\r
128 TRDYn : In std_logic;\r
129 INT_REG : Out std_logic_vector (7 downto 0);\r
130 INTAn : Out std_logic;\r
131 PCI_INTAn : Out std_logic );\r
132 end component;\r
133\r
134 component FIFO_CONTROL\r
135 Port ( FIFO_RDn : In std_logic;\r
136 FLAG_IN_0 : In std_logic;\r
137 FLAG_IN_4 : In std_logic;\r
138 HOLD : In std_logic;\r
139 KONST_1 : In std_logic;\r
140 PCI_CLOCK : In std_logic;\r
141 PSC_ENABLE : In std_logic;\r
142 R_EFn : In std_logic;\r
143 R_FFn : In std_logic;\r
144 R_HFn : In std_logic;\r
145 RESET : In std_logic;\r
146 S_EFn : In std_logic;\r
147 S_FFn : In std_logic;\r
148 S_FIFO_Q_OUT : In std_logic_vector (7 downto 0);\r
149 S_HFn : In std_logic;\r
150 SERIAL_IN : In std_logic;\r
151 SPC_ENABLE : In std_logic;\r
152 SPC_RDY_IN : In std_logic;\r
153 WRITE_XX1_0 : In std_logic;\r
154 R_ERROR : Out std_logic;\r
155 R_FIFO_D_IN : Out std_logic_vector (7 downto 0);\r
156 R_FIFO_READn : Out std_logic;\r
157 R_FIFO_RESETn : Out std_logic;\r
158 R_FIFO_RETRANSMITn : Out std_logic;\r
159 R_FIFO_WRITEn : Out std_logic;\r
160 RESERVE : Out std_logic;\r
161 S_ERROR : Out std_logic;\r
162 S_FIFO_READn : Out std_logic;\r
163 S_FIFO_RESETn : Out std_logic;\r
164 S_FIFO_RETRANSMITn : Out std_logic;\r
165 S_FIFO_WRITEn : Out std_logic;\r
166 SERIAL_OUT : Out std_logic;\r
167 SPC_RDY_OUT : Out std_logic;\r
168 SR_ERROR : Out std_logic;\r
169 SYNC_FLAG : Out std_logic_vector (7 downto 0) );\r
170 end component;\r
171\r
172 component PCI_TOP\r
173 Port ( FLAG : In std_logic_vector (7 downto 0);\r
174 INT_REG : In std_logic_vector (7 downto 0);\r
175 PCI_CBEn : In std_logic_vector (3 downto 0);\r
176 PCI_CLOCK : In std_logic;\r
177 PCI_FRAMEn : In std_logic;\r
178 PCI_IDSEL : In std_logic;\r
179 PCI_IRDYn : In std_logic;\r
180 PCI_RSTn : In std_logic;\r
181 R_FIFO_Q : In std_logic_vector (7 downto 0);\r
182 REVISON_ID : In std_logic_vector (7 downto 0);\r
183 VENDOR_ID : In std_logic_vector (15 downto 0);\r
184 PCI_AD : InOut std_logic_vector (31 downto 0);\r
185 PCI_PAR : InOut std_logic;\r
186 AD_REG : Out std_logic_vector (31 downto 0);\r
187 DEVSELn : Out std_logic;\r
188 FIFO_RDn : Out std_logic;\r
189 PCI_DEVSELn : Out std_logic;\r
190 PCI_PERRn : Out std_logic;\r
191 PCI_SERRn : Out std_logic;\r
192 PCI_STOPn : Out std_logic;\r
193 PCI_TRDYn : Out std_logic;\r
194 READ_SEL : Out std_logic_vector (1 downto 0);\r
195 READ_XX1_0 : Out std_logic;\r
196 READ_XX3_2 : Out std_logic;\r
197 READ_XX5_4 : Out std_logic;\r
198 READ_XX7_6 : Out std_logic;\r
199 REG_OUT_XX0 : Out std_logic_vector (7 downto 0);\r
200 REG_OUT_XX6 : Out std_logic_vector (7 downto 0);\r
201 REG_OUT_XX7 : Out std_logic_vector (7 downto 0);\r
202 TRDYn : Out std_logic;\r
203 WRITE_XX1_0 : Out std_logic;\r
204 WRITE_XX3_2 : Out std_logic;\r
205 WRITE_XX5_4 : Out std_logic;\r
206 WRITE_XX7_6 : Out std_logic );\r
207 end component;\r
208\r
209component fifo_generator_v3_2\r
210 port (\r
211 clk: IN std_logic;\r
212 din: IN std_logic_VECTOR(7 downto 0);\r
213 rd_en: IN std_logic;\r
214 rst: IN std_logic;\r
215 wr_en: IN std_logic;\r
216 almost_empty: OUT std_logic;\r
217 almost_full: OUT std_logic;\r
218 dout: OUT std_logic_VECTOR(7 downto 0);\r
219 empty: OUT std_logic;\r
220 full: OUT std_logic;\r
221 prog_full: OUT std_logic);\r
222end component;\r
223\r
224begin\r
225 SERIAL_IN <= SERIAL_OUT;\r
226 SPC_RDY_IN <= SPC_RDY_OUT;\r
227 LED_2 <= TAST_RESn;\r
228 LED_3 <= TAST_SETn;\r
229 LED_4 <= '0';\r
230 LED_5 <= not watch;\r
231 PCI_INTAn <= watch;\r
232\r
233 I19 : MESS_1_TB\r
234 Port Map ( DEVSELn=>DEVSELn, INTAn=>INTAn, KONST_1=>KONST_1,\r
235 PCI_IDSEL=>PCI_IDSEL,\r
236 REG_OUT_XX7(7 downto 0)=>REG_OUT_XX7(7 downto 0),\r
237 TB_DEVSELn=>TB_nDEVSEL, TB_INTAn=>TB_nINTA,\r
238 TB_PCI_IDSEL=>TB_IDSEL );\r
239 I18 : VEN_REV_ID\r
240 Port Map ( REV_ID(7 downto 0)=>REVISON_ID(7 downto 0),\r
241 VEN_ID(15 downto 0)=>VENDOR_ID(15 downto 0) );\r
242 I16 : INTERRUPT\r
243 Port Map ( INT_IN_0=>SYNC_FLAG(1), INT_IN_1=>SYNC_FLAG(6),\r
244 INT_IN_2=>KONST_1, INT_IN_3=>KONST_1, INT_IN_4=>KONST_1,\r
245 INT_IN_5=>KONST_1, INT_IN_6=>KONST_1, INT_IN_7=>KONST_1,\r
246 INT_MASKE(7 downto 0)=>REG_OUT_XX6(7 downto 0),\r
247 INT_RES(7 downto 0)=>AD_REG(7 downto 0),\r
248 PCI_CLOCK=>PCI_CLOCK, PCI_RSTn=>PCI_RSTn,\r
249 READ_XX5_4=>READ_XX5_4, RESET=>REG_OUT_XX7(0),\r
250 TAST_RESn=>TAST_RESn, TAST_SETn=>TAST_SETn,\r
251 TRDYn=>TRDYn, INT_REG(7 downto 0)=>INT_REG(7 downto 0),\r
252 INTAn=>INTAn, PCI_INTAn=>watch);\r
253 I14 : FIFO_CONTROL\r
254 Port Map ( FIFO_RDn=>FIFO_RDn, FLAG_IN_0=>R_ERROR,\r
255 FLAG_IN_4=>S_ERROR, HOLD=>READ_SEL(0), KONST_1=>KONST_1,\r
256 PCI_CLOCK=>PCI_CLOCK, PSC_ENABLE=>REG_OUT_XX7(1),\r
257 R_EFn=>R_EFn, R_FFn=>R_FFn, R_HFn=>R_HFn,\r
258 RESET=>REG_OUT_XX7(0), S_EFn=>S_EFn, S_FFn=>S_FFn,\r
259 S_FIFO_Q_OUT(7 downto 0)=>S_FIFO_Q_OUT(7 downto 0),\r
260 S_HFn=>S_HFn, SERIAL_IN=>SERIAL_IN,\r
261 SPC_ENABLE=>REG_OUT_XX7(2), SPC_RDY_IN=>SPC_RDY_IN,\r
262 WRITE_XX1_0=>WRITE_XX1_0, R_ERROR=>R_ERROR,\r
263 R_FIFO_D_IN(7 downto 0)=>R_FIFO_D_IN(7 downto 0),\r
264 R_FIFO_READn=>R_FIFO_READn,\r
265 R_FIFO_RESETn=>R_FIFO_RESETn,\r
266 R_FIFO_RETRANSMITn=>R_FIFO_RTn,\r
267 R_FIFO_WRITEn=>R_FIFO_WRITEn, RESERVE=>RESERVE,\r
268 S_ERROR=>S_ERROR, S_FIFO_READn=>S_FIFO_READn,\r
269 S_FIFO_RESETn=>S_FIFO_RESETn,\r
270 S_FIFO_RETRANSMITn=>S_FIFO_RTn,\r
271 S_FIFO_WRITEn=>S_FIFO_WRITEn, SERIAL_OUT=>SERIAL_OUT,\r
272 SPC_RDY_OUT=>SPC_RDY_OUT, SR_ERROR=>SR_ERROR,\r
273 SYNC_FLAG(7 downto 0)=>SYNC_FLAG(7 downto 0) );\r
274 I1 : PCI_TOP\r
275 Port Map ( FLAG(7 downto 0)=>SYNC_FLAG(7 downto 0),\r
276 INT_REG(7 downto 0)=>INT_REG(7 downto 0),\r
277 PCI_CBEn(3 downto 0)=>PCI_CBEn(3 downto 0),\r
278 PCI_CLOCK=>PCI_CLOCK, PCI_FRAMEn=>PCI_FRAMEn,\r
279 PCI_IDSEL=>PCI_IDSEL, PCI_IRDYn=>PCI_IRDYn,\r
280 PCI_RSTn=>PCI_RSTn,\r
281 R_FIFO_Q(7 downto 0)=>R_FIFO_Q_OUT(7 downto 0),\r
282 REVISON_ID(7 downto 0)=>REVISON_ID(7 downto 0),\r
283 VENDOR_ID(15 downto 0)=>VENDOR_ID(15 downto 0),\r
284 PCI_AD(31 downto 0)=>PCI_AD(31 downto 0),\r
285 PCI_PAR=>PCI_PAR,\r
286 AD_REG(31 downto 0)=>AD_REG(31 downto 0),\r
287 DEVSELn=>DEVSELn, FIFO_RDn=>FIFO_RDn,\r
288 PCI_DEVSELn=>PCI_DEVSELn, PCI_PERRn=>PCI_PERRn,\r
289 PCI_SERRn=>PCI_SERRn, PCI_STOPn=>PCI_STOPn,\r
290 PCI_TRDYn=>PCI_TRDYn,\r
291 READ_SEL(1 downto 0)=>READ_SEL(1 downto 0),\r
292 READ_XX1_0=>READ_XX1_0, READ_XX3_2=>READ_XX3_2,\r
293 READ_XX5_4=>READ_XX5_4, READ_XX7_6=>READ_XX7_6,\r
294 REG_OUT_XX0(7 downto 0)=>S_FIFO_D_IN(7 downto 0),\r
295 REG_OUT_XX6(7 downto 0)=>REG_OUT_XX6(7 downto 0),\r
296 REG_OUT_XX7(7 downto 0)=>REG_OUT_XX7(7 downto 0),\r
297 TRDYn=>TRDYn, WRITE_XX1_0=>WRITE_XX1_0,\r
298 WRITE_XX3_2=>WRITE_XX3_2, WRITE_XX5_4=>WRITE_XX5_4,\r
299 WRITE_XX7_6=>WRITE_XX7_6 );\r
300\r
301receive_fifo : fifo_generator_v3_2\r
302 port map (\r
303 clk => PCI_CLOCK,\r
304 din => R_FIFO_D_IN,\r
305 rd_en => not R_FIFO_READn,\r
306 rst => not R_FIFO_RESETn,\r
307 wr_en => not R_FIFO_WRITEn,\r
308 dout => R_FIFO_Q_OUT,\r
309 empty => R_EFn,\r
310 full => R_FFn,\r
311 prog_full => R_HFn);\r
312\r
313send_fifo : fifo_generator_v3_2\r
314 port map (\r
315 clk => PCI_CLOCK,\r
316 din => S_FIFO_D_IN,\r
317 rd_en => not S_FIFO_READn,\r
318 rst => not S_FIFO_RESETn,\r
319 wr_en => not S_FIFO_WRITEn,\r
320 dout => S_FIFO_Q_OUT,\r
321 empty => S_EFn,\r
322 full => S_FFn,\r
323 prog_full => S_HFn);\r
324end SCHEMATIC;\r
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