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1module disp_dec(disp_dec_in, disp_dec_out);\r
2 input [3:0] disp_dec_in;\r
3 output reg [6:0] disp_dec_out;\r
4\r
5 always @(disp_dec_in)\r
6 begin\r
7 case (disp_dec_in)\r
8 4'b0000: disp_dec_out <= 7'b1000000;\r
9 4'b0001: disp_dec_out <= 7'b1111001;\r
10 4'b0010: disp_dec_out <= 7'b0100100;\r
11 4'b0011: disp_dec_out <= 7'b0110000;\r
12\r
13 4'b0100: disp_dec_out <= 7'b0011001;\r
14 4'b0101: disp_dec_out <= 7'b0010010;\r
15 4'b0110: disp_dec_out <= 7'b0000010;\r
16 4'b0111: disp_dec_out <= 7'b1111000;\r
17\r
18 4'b1000: disp_dec_out <= 7'b0000000;\r
19 4'b1001: disp_dec_out <= 7'b0010000;\r
20 4'b1010: disp_dec_out <= 7'b0001000;\r
21 4'b1011: disp_dec_out <= 7'b0000011;\r
22\r
23 4'b1100: disp_dec_out <= 7'b1000110;\r
24 4'b1101: disp_dec_out <= 7'b0100001;\r
25 4'b1110: disp_dec_out <= 7'b0000110;\r
26 4'b1111: disp_dec_out <= 7'b0001110;\r
27 endcase\r
28 end\r
29endmodule\r
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