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1 | ////////////////////////////////////////////////////////////////////// | |
2 | //// //// | |
3 | //// eth_registers.v //// | |
4 | //// //// | |
5 | //// This file is part of the Ethernet IP core project //// | |
6 | //// http://www.opencores.org/projects/ethmac/ //// | |
7 | //// //// | |
8 | //// Author(s): //// | |
9 | //// - Igor Mohor (igorM@opencores.org) //// | |
10 | //// //// | |
11 | //// All additional information is avaliable in the Readme.txt //// | |
12 | //// file. //// | |
13 | //// //// | |
14 | ////////////////////////////////////////////////////////////////////// | |
15 | //// //// | |
16 | //// Copyright (C) 2001, 2002 Authors //// | |
17 | //// //// | |
18 | //// This source file may be used and distributed without //// | |
19 | //// restriction provided that this copyright statement is not //// | |
20 | //// removed from the file and that any derivative work contains //// | |
21 | //// the original copyright notice and the associated disclaimer. //// | |
22 | //// //// | |
23 | //// This source file is free software; you can redistribute it //// | |
24 | //// and/or modify it under the terms of the GNU Lesser General //// | |
25 | //// Public License as published by the Free Software Foundation; //// | |
26 | //// either version 2.1 of the License, or (at your option) any //// | |
27 | //// later version. //// | |
28 | //// //// | |
29 | //// This source is distributed in the hope that it will be //// | |
30 | //// useful, but WITHOUT ANY WARRANTY; without even the implied //// | |
31 | //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// | |
32 | //// PURPOSE. See the GNU Lesser General Public License for more //// | |
33 | //// details. //// | |
34 | //// //// | |
35 | //// You should have received a copy of the GNU Lesser General //// | |
36 | //// Public License along with this source; if not, download it //// | |
37 | //// from http://www.opencores.org/lgpl.shtml //// | |
38 | //// //// | |
39 | ////////////////////////////////////////////////////////////////////// | |
40 | // | |
41 | // CVS Revision History | |
42 | // | |
43 | // $Log: eth_registers.v,v $ | |
44 | // Revision 1.1 2007-03-20 17:50:56 sithglan | |
45 | // add shit | |
46 | // | |
47 | // Revision 1.29 2005/03/21 20:07:18 igorm | |
48 | // Some small fixes + some troubles fixed. | |
49 | // | |
50 | // Revision 1.28 2004/04/26 15:26:23 igorm | |
51 | // - Bug connected to the TX_BD_NUM_Wr signal fixed (bug came in with the | |
52 | // previous update of the core. | |
53 | // - TxBDAddress is set to 0 after the TX is enabled in the MODER register. | |
54 | // - RxBDAddress is set to r_TxBDNum<<1 after the RX is enabled in the MODER | |
55 | // register. (thanks to Mathias and Torbjorn) | |
56 | // - Multicast reception was fixed. Thanks to Ulrich Gries | |
57 | // | |
58 | // Revision 1.27 2004/04/26 11:42:17 igorm | |
59 | // TX_BD_NUM_Wr error fixed. Error was entered with the last check-in. | |
60 | // | |
61 | // Revision 1.26 2003/11/12 18:24:59 tadejm | |
62 | // WISHBONE slave changed and tested from only 32-bit accesss to byte access. | |
63 | // | |
64 | // Revision 1.25 2003/04/18 16:26:25 mohor | |
65 | // RxBDAddress was updated also when value to r_TxBDNum was written with | |
66 | // greater value than allowed. | |
67 | // | |
68 | // Revision 1.24 2002/11/22 01:57:06 mohor | |
69 | // Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort | |
70 | // synchronized. | |
71 | // | |
72 | // Revision 1.23 2002/11/19 18:13:49 mohor | |
73 | // r_MiiMRst is not used for resetting the MIIM module. wb_rst used instead. | |
74 | // | |
75 | // Revision 1.22 2002/11/14 18:37:20 mohor | |
76 | // r_Rst signal does not reset any module any more and is removed from the design. | |
77 | // | |
78 | // Revision 1.21 2002/09/10 10:35:23 mohor | |
79 | // Ethernet debug registers removed. | |
80 | // | |
81 | // Revision 1.20 2002/09/04 18:40:25 mohor | |
82 | // ETH_TXCTRL and ETH_RXCTRL registers added. Interrupts related to | |
83 | // the control frames connected. | |
84 | // | |
85 | // Revision 1.19 2002/08/19 16:01:40 mohor | |
86 | // Only values smaller or equal to 0x80 can be written to TX_BD_NUM register. | |
87 | // r_TxEn and r_RxEn depend on the limit values of the TX_BD_NUMOut. | |
88 | // | |
89 | // Revision 1.18 2002/08/16 22:28:23 mohor | |
90 | // Syntax error fixed. | |
91 | // | |
92 | // Revision 1.17 2002/08/16 22:23:03 mohor | |
93 | // Syntax error fixed. | |
94 | // | |
95 | // Revision 1.16 2002/08/16 22:14:22 mohor | |
96 | // Synchronous reset added to all registers. Defines used for width. r_MiiMRst | |
97 | // changed from bit position 10 to 9. | |
98 | // | |
99 | // Revision 1.15 2002/08/14 18:26:37 mohor | |
100 | // LinkFailRegister is reflecting the status of the PHY's link fail status bit. | |
101 | // | |
102 | // Revision 1.14 2002/04/22 14:03:44 mohor | |
103 | // Interrupts are visible in the ETH_INT_SOURCE regardless if they are enabled | |
104 | // or not. | |
105 | // | |
106 | // Revision 1.13 2002/02/26 16:18:09 mohor | |
107 | // Reset values are passed to registers through parameters | |
108 | // | |
109 | // Revision 1.12 2002/02/17 13:23:42 mohor | |
110 | // Define missmatch fixed. | |
111 | // | |
112 | // Revision 1.11 2002/02/16 14:03:44 mohor | |
113 | // Registered trimmed. Unused registers removed. | |
114 | // | |
115 | // Revision 1.10 2002/02/15 11:08:25 mohor | |
116 | // File format fixed a bit. | |
117 | // | |
118 | // Revision 1.9 2002/02/14 20:19:41 billditt | |
119 | // Modified for Address Checking, | |
120 | // addition of eth_addrcheck.v | |
121 | // | |
122 | // Revision 1.8 2002/02/12 17:01:19 mohor | |
123 | // HASH0 and HASH1 registers added. | |
124 | ||
125 | // Revision 1.7 2002/01/23 10:28:16 mohor | |
126 | // Link in the header changed. | |
127 | // | |
128 | // Revision 1.6 2001/12/05 15:00:16 mohor | |
129 | // RX_BD_NUM changed to TX_BD_NUM (holds number of TX descriptors | |
130 | // instead of the number of RX descriptors). | |
131 | // | |
132 | // Revision 1.5 2001/12/05 10:22:19 mohor | |
133 | // ETH_RX_BD_ADR register deleted. ETH_RX_BD_NUM is used instead. | |
134 | // | |
135 | // Revision 1.4 2001/10/19 08:43:51 mohor | |
136 | // eth_timescale.v changed to timescale.v This is done because of the | |
137 | // simulation of the few cores in a one joined project. | |
138 | // | |
139 | // Revision 1.3 2001/10/18 12:07:11 mohor | |
140 | // Status signals changed, Adress decoding changed, interrupt controller | |
141 | // added. | |
142 | // | |
143 | // Revision 1.2 2001/09/24 15:02:56 mohor | |
144 | // Defines changed (All precede with ETH_). Small changes because some | |
145 | // tools generate warnings when two operands are together. Synchronization | |
146 | // between two clocks domains in eth_wishbonedma.v is changed (due to ASIC | |
147 | // demands). | |
148 | // | |
149 | // Revision 1.1 2001/08/06 14:44:29 mohor | |
150 | // A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex). | |
151 | // Include files fixed to contain no path. | |
152 | // File names and module names changed ta have a eth_ prologue in the name. | |
153 | // File eth_timescale.v is used to define timescale | |
154 | // All pin names on the top module are changed to contain _I, _O or _OE at the end. | |
155 | // Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O | |
156 | // and Mdo_OE. The bidirectional signal must be created on the top level. This | |
157 | // is done due to the ASIC tools. | |
158 | // | |
159 | // Revision 1.2 2001/08/02 09:25:31 mohor | |
160 | // Unconnected signals are now connected. | |
161 | // | |
162 | // Revision 1.1 2001/07/30 21:23:42 mohor | |
163 | // Directory structure changed. Files checked and joind together. | |
164 | // | |
165 | // | |
166 | // | |
167 | // | |
168 | // | |
169 | // | |
170 | ||
171 | `include "eth_defines.v" | |
172 | `include "timescale.v" | |
173 | ||
174 | ||
175 | module eth_registers( DataIn, Address, Rw, Cs, Clk, Reset, DataOut, | |
176 | r_RecSmall, r_Pad, r_HugEn, r_CrcEn, r_DlyCrcEn, | |
177 | r_FullD, r_ExDfrEn, r_NoBckof, r_LoopBck, r_IFG, | |
178 | r_Pro, r_Iam, r_Bro, r_NoPre, r_TxEn, r_RxEn, | |
179 | TxB_IRQ, TxE_IRQ, RxB_IRQ, RxE_IRQ, Busy_IRQ, | |
180 | r_IPGT, r_IPGR1, r_IPGR2, r_MinFL, r_MaxFL, r_MaxRet, | |
181 | r_CollValid, r_TxFlow, r_RxFlow, r_PassAll, | |
182 | r_MiiNoPre, r_ClkDiv, r_WCtrlData, r_RStat, r_ScanStat, | |
183 | r_RGAD, r_FIAD, r_CtrlData, NValid_stat, Busy_stat, | |
184 | LinkFail, r_MAC, WCtrlDataStart, RStatStart, | |
185 | UpdateMIIRX_DATAReg, Prsd, r_TxBDNum, int_o, | |
186 | r_HASH0, r_HASH1, r_TxPauseTV, r_TxPauseRq, RstTxPauseRq, TxCtrlEndFrm, | |
187 | StartTxDone, TxClk, RxClk, SetPauseTimer | |
188 | ); | |
189 | ||
190 | parameter Tp = 1; | |
191 | ||
192 | input [31:0] DataIn; | |
193 | input [7:0] Address; | |
194 | ||
195 | input Rw; | |
196 | input [3:0] Cs; | |
197 | input Clk; | |
198 | input Reset; | |
199 | ||
200 | input WCtrlDataStart; | |
201 | input RStatStart; | |
202 | ||
203 | input UpdateMIIRX_DATAReg; | |
204 | input [15:0] Prsd; | |
205 | ||
206 | output [31:0] DataOut; | |
207 | reg [31:0] DataOut; | |
208 | ||
209 | output r_RecSmall; | |
210 | output r_Pad; | |
211 | output r_HugEn; | |
212 | output r_CrcEn; | |
213 | output r_DlyCrcEn; | |
214 | output r_FullD; | |
215 | output r_ExDfrEn; | |
216 | output r_NoBckof; | |
217 | output r_LoopBck; | |
218 | output r_IFG; | |
219 | output r_Pro; | |
220 | output r_Iam; | |
221 | output r_Bro; | |
222 | output r_NoPre; | |
223 | output r_TxEn; | |
224 | output r_RxEn; | |
225 | output [31:0] r_HASH0; | |
226 | output [31:0] r_HASH1; | |
227 | ||
228 | input TxB_IRQ; | |
229 | input TxE_IRQ; | |
230 | input RxB_IRQ; | |
231 | input RxE_IRQ; | |
232 | input Busy_IRQ; | |
233 | ||
234 | output [6:0] r_IPGT; | |
235 | ||
236 | output [6:0] r_IPGR1; | |
237 | ||
238 | output [6:0] r_IPGR2; | |
239 | ||
240 | output [15:0] r_MinFL; | |
241 | output [15:0] r_MaxFL; | |
242 | ||
243 | output [3:0] r_MaxRet; | |
244 | output [5:0] r_CollValid; | |
245 | ||
246 | output r_TxFlow; | |
247 | output r_RxFlow; | |
248 | output r_PassAll; | |
249 | ||
250 | output r_MiiNoPre; | |
251 | output [7:0] r_ClkDiv; | |
252 | ||
253 | output r_WCtrlData; | |
254 | output r_RStat; | |
255 | output r_ScanStat; | |
256 | ||
257 | output [4:0] r_RGAD; | |
258 | output [4:0] r_FIAD; | |
259 | ||
260 | output [15:0]r_CtrlData; | |
261 | ||
262 | ||
263 | input NValid_stat; | |
264 | input Busy_stat; | |
265 | input LinkFail; | |
266 | ||
267 | output [47:0]r_MAC; | |
268 | output [7:0] r_TxBDNum; | |
269 | output int_o; | |
270 | output [15:0]r_TxPauseTV; | |
271 | output r_TxPauseRq; | |
272 | input RstTxPauseRq; | |
273 | input TxCtrlEndFrm; | |
274 | input StartTxDone; | |
275 | input TxClk; | |
276 | input RxClk; | |
277 | input SetPauseTimer; | |
278 | ||
279 | reg irq_txb; | |
280 | reg irq_txe; | |
281 | reg irq_rxb; | |
282 | reg irq_rxe; | |
283 | reg irq_busy; | |
284 | reg irq_txc; | |
285 | reg irq_rxc; | |
286 | ||
287 | reg SetTxCIrq_txclk; | |
288 | reg SetTxCIrq_sync1, SetTxCIrq_sync2, SetTxCIrq_sync3; | |
289 | reg SetTxCIrq; | |
290 | reg ResetTxCIrq_sync1, ResetTxCIrq_sync2; | |
291 | ||
292 | reg SetRxCIrq_rxclk; | |
293 | reg SetRxCIrq_sync1, SetRxCIrq_sync2, SetRxCIrq_sync3; | |
294 | reg SetRxCIrq; | |
295 | reg ResetRxCIrq_sync1; | |
296 | reg ResetRxCIrq_sync2; | |
297 | reg ResetRxCIrq_sync3; | |
298 | ||
299 | wire [3:0] Write = Cs & {4{Rw}}; | |
300 | wire Read = (|Cs) & ~Rw; | |
301 | ||
302 | wire MODER_Sel = (Address == `ETH_MODER_ADR ); | |
303 | wire INT_SOURCE_Sel = (Address == `ETH_INT_SOURCE_ADR ); | |
304 | wire INT_MASK_Sel = (Address == `ETH_INT_MASK_ADR ); | |
305 | wire IPGT_Sel = (Address == `ETH_IPGT_ADR ); | |
306 | wire IPGR1_Sel = (Address == `ETH_IPGR1_ADR ); | |
307 | wire IPGR2_Sel = (Address == `ETH_IPGR2_ADR ); | |
308 | wire PACKETLEN_Sel = (Address == `ETH_PACKETLEN_ADR ); | |
309 | wire COLLCONF_Sel = (Address == `ETH_COLLCONF_ADR ); | |
310 | ||
311 | wire CTRLMODER_Sel = (Address == `ETH_CTRLMODER_ADR ); | |
312 | wire MIIMODER_Sel = (Address == `ETH_MIIMODER_ADR ); | |
313 | wire MIICOMMAND_Sel = (Address == `ETH_MIICOMMAND_ADR ); | |
314 | wire MIIADDRESS_Sel = (Address == `ETH_MIIADDRESS_ADR ); | |
315 | wire MIITX_DATA_Sel = (Address == `ETH_MIITX_DATA_ADR ); | |
316 | wire MAC_ADDR0_Sel = (Address == `ETH_MAC_ADDR0_ADR ); | |
317 | wire MAC_ADDR1_Sel = (Address == `ETH_MAC_ADDR1_ADR ); | |
318 | wire HASH0_Sel = (Address == `ETH_HASH0_ADR ); | |
319 | wire HASH1_Sel = (Address == `ETH_HASH1_ADR ); | |
320 | wire TXCTRL_Sel = (Address == `ETH_TX_CTRL_ADR ); | |
321 | wire RXCTRL_Sel = (Address == `ETH_RX_CTRL_ADR ); | |
322 | wire TX_BD_NUM_Sel = (Address == `ETH_TX_BD_NUM_ADR ); | |
323 | ||
324 | ||
325 | wire [2:0] MODER_Wr; | |
326 | wire [0:0] INT_SOURCE_Wr; | |
327 | wire [0:0] INT_MASK_Wr; | |
328 | wire [0:0] IPGT_Wr; | |
329 | wire [0:0] IPGR1_Wr; | |
330 | wire [0:0] IPGR2_Wr; | |
331 | wire [3:0] PACKETLEN_Wr; | |
332 | wire [2:0] COLLCONF_Wr; | |
333 | wire [0:0] CTRLMODER_Wr; | |
334 | wire [1:0] MIIMODER_Wr; | |
335 | wire [0:0] MIICOMMAND_Wr; | |
336 | wire [1:0] MIIADDRESS_Wr; | |
337 | wire [1:0] MIITX_DATA_Wr; | |
338 | wire MIIRX_DATA_Wr; | |
339 | wire [3:0] MAC_ADDR0_Wr; | |
340 | wire [1:0] MAC_ADDR1_Wr; | |
341 | wire [3:0] HASH0_Wr; | |
342 | wire [3:0] HASH1_Wr; | |
343 | wire [2:0] TXCTRL_Wr; | |
344 | wire [0:0] TX_BD_NUM_Wr; | |
345 | ||
346 | assign MODER_Wr[0] = Write[0] & MODER_Sel; | |
347 | assign MODER_Wr[1] = Write[1] & MODER_Sel; | |
348 | assign MODER_Wr[2] = Write[2] & MODER_Sel; | |
349 | assign INT_SOURCE_Wr[0] = Write[0] & INT_SOURCE_Sel; | |
350 | assign INT_MASK_Wr[0] = Write[0] & INT_MASK_Sel; | |
351 | assign IPGT_Wr[0] = Write[0] & IPGT_Sel; | |
352 | assign IPGR1_Wr[0] = Write[0] & IPGR1_Sel; | |
353 | assign IPGR2_Wr[0] = Write[0] & IPGR2_Sel; | |
354 | assign PACKETLEN_Wr[0] = Write[0] & PACKETLEN_Sel; | |
355 | assign PACKETLEN_Wr[1] = Write[1] & PACKETLEN_Sel; | |
356 | assign PACKETLEN_Wr[2] = Write[2] & PACKETLEN_Sel; | |
357 | assign PACKETLEN_Wr[3] = Write[3] & PACKETLEN_Sel; | |
358 | assign COLLCONF_Wr[0] = Write[0] & COLLCONF_Sel; | |
359 | assign COLLCONF_Wr[1] = 1'b0; // Not used | |
360 | assign COLLCONF_Wr[2] = Write[2] & COLLCONF_Sel; | |
361 | ||
362 | assign CTRLMODER_Wr[0] = Write[0] & CTRLMODER_Sel; | |
363 | assign MIIMODER_Wr[0] = Write[0] & MIIMODER_Sel; | |
364 | assign MIIMODER_Wr[1] = Write[1] & MIIMODER_Sel; | |
365 | assign MIICOMMAND_Wr[0] = Write[0] & MIICOMMAND_Sel; | |
366 | assign MIIADDRESS_Wr[0] = Write[0] & MIIADDRESS_Sel; | |
367 | assign MIIADDRESS_Wr[1] = Write[1] & MIIADDRESS_Sel; | |
368 | assign MIITX_DATA_Wr[0] = Write[0] & MIITX_DATA_Sel; | |
369 | assign MIITX_DATA_Wr[1] = Write[1] & MIITX_DATA_Sel; | |
370 | assign MIIRX_DATA_Wr = UpdateMIIRX_DATAReg; | |
371 | assign MAC_ADDR0_Wr[0] = Write[0] & MAC_ADDR0_Sel; | |
372 | assign MAC_ADDR0_Wr[1] = Write[1] & MAC_ADDR0_Sel; | |
373 | assign MAC_ADDR0_Wr[2] = Write[2] & MAC_ADDR0_Sel; | |
374 | assign MAC_ADDR0_Wr[3] = Write[3] & MAC_ADDR0_Sel; | |
375 | assign MAC_ADDR1_Wr[0] = Write[0] & MAC_ADDR1_Sel; | |
376 | assign MAC_ADDR1_Wr[1] = Write[1] & MAC_ADDR1_Sel; | |
377 | assign HASH0_Wr[0] = Write[0] & HASH0_Sel; | |
378 | assign HASH0_Wr[1] = Write[1] & HASH0_Sel; | |
379 | assign HASH0_Wr[2] = Write[2] & HASH0_Sel; | |
380 | assign HASH0_Wr[3] = Write[3] & HASH0_Sel; | |
381 | assign HASH1_Wr[0] = Write[0] & HASH1_Sel; | |
382 | assign HASH1_Wr[1] = Write[1] & HASH1_Sel; | |
383 | assign HASH1_Wr[2] = Write[2] & HASH1_Sel; | |
384 | assign HASH1_Wr[3] = Write[3] & HASH1_Sel; | |
385 | assign TXCTRL_Wr[0] = Write[0] & TXCTRL_Sel; | |
386 | assign TXCTRL_Wr[1] = Write[1] & TXCTRL_Sel; | |
387 | assign TXCTRL_Wr[2] = Write[2] & TXCTRL_Sel; | |
388 | assign TX_BD_NUM_Wr[0] = Write[0] & TX_BD_NUM_Sel & (DataIn<='h80); | |
389 | ||
390 | ||
391 | ||
392 | wire [31:0] MODEROut; | |
393 | wire [31:0] INT_SOURCEOut; | |
394 | wire [31:0] INT_MASKOut; | |
395 | wire [31:0] IPGTOut; | |
396 | wire [31:0] IPGR1Out; | |
397 | wire [31:0] IPGR2Out; | |
398 | wire [31:0] PACKETLENOut; | |
399 | wire [31:0] COLLCONFOut; | |
400 | wire [31:0] CTRLMODEROut; | |
401 | wire [31:0] MIIMODEROut; | |
402 | wire [31:0] MIICOMMANDOut; | |
403 | wire [31:0] MIIADDRESSOut; | |
404 | wire [31:0] MIITX_DATAOut; | |
405 | wire [31:0] MIIRX_DATAOut; | |
406 | wire [31:0] MIISTATUSOut; | |
407 | wire [31:0] MAC_ADDR0Out; | |
408 | wire [31:0] MAC_ADDR1Out; | |
409 | wire [31:0] TX_BD_NUMOut; | |
410 | wire [31:0] HASH0Out; | |
411 | wire [31:0] HASH1Out; | |
412 | wire [31:0] TXCTRLOut; | |
413 | ||
414 | // MODER Register | |
415 | eth_register #(`ETH_MODER_WIDTH_0, `ETH_MODER_DEF_0) MODER_0 | |
416 | ( | |
417 | .DataIn (DataIn[`ETH_MODER_WIDTH_0 - 1:0]), | |
418 | .DataOut (MODEROut[`ETH_MODER_WIDTH_0 - 1:0]), | |
419 | .Write (MODER_Wr[0]), | |
420 | .Clk (Clk), | |
421 | .Reset (Reset), | |
422 | .SyncReset (1'b0) | |
423 | ); | |
424 | eth_register #(`ETH_MODER_WIDTH_1, `ETH_MODER_DEF_1) MODER_1 | |
425 | ( | |
426 | .DataIn (DataIn[`ETH_MODER_WIDTH_1 + 7:8]), | |
427 | .DataOut (MODEROut[`ETH_MODER_WIDTH_1 + 7:8]), | |
428 | .Write (MODER_Wr[1]), | |
429 | .Clk (Clk), | |
430 | .Reset (Reset), | |
431 | .SyncReset (1'b0) | |
432 | ); | |
433 | eth_register #(`ETH_MODER_WIDTH_2, `ETH_MODER_DEF_2) MODER_2 | |
434 | ( | |
435 | .DataIn (DataIn[`ETH_MODER_WIDTH_2 + 15:16]), | |
436 | .DataOut (MODEROut[`ETH_MODER_WIDTH_2 + 15:16]), | |
437 | .Write (MODER_Wr[2]), | |
438 | .Clk (Clk), | |
439 | .Reset (Reset), | |
440 | .SyncReset (1'b0) | |
441 | ); | |
442 | assign MODEROut[31:`ETH_MODER_WIDTH_2 + 16] = 0; | |
443 | ||
444 | // INT_MASK Register | |
445 | eth_register #(`ETH_INT_MASK_WIDTH_0, `ETH_INT_MASK_DEF_0) INT_MASK_0 | |
446 | ( | |
447 | .DataIn (DataIn[`ETH_INT_MASK_WIDTH_0 - 1:0]), | |
448 | .DataOut (INT_MASKOut[`ETH_INT_MASK_WIDTH_0 - 1:0]), | |
449 | .Write (INT_MASK_Wr[0]), | |
450 | .Clk (Clk), | |
451 | .Reset (Reset), | |
452 | .SyncReset (1'b0) | |
453 | ); | |
454 | assign INT_MASKOut[31:`ETH_INT_MASK_WIDTH_0] = 0; | |
455 | ||
456 | // IPGT Register | |
457 | eth_register #(`ETH_IPGT_WIDTH_0, `ETH_IPGT_DEF_0) IPGT_0 | |
458 | ( | |
459 | .DataIn (DataIn[`ETH_IPGT_WIDTH_0 - 1:0]), | |
460 | .DataOut (IPGTOut[`ETH_IPGT_WIDTH_0 - 1:0]), | |
461 | .Write (IPGT_Wr[0]), | |
462 | .Clk (Clk), | |
463 | .Reset (Reset), | |
464 | .SyncReset (1'b0) | |
465 | ); | |
466 | assign IPGTOut[31:`ETH_IPGT_WIDTH_0] = 0; | |
467 | ||
468 | // IPGR1 Register | |
469 | eth_register #(`ETH_IPGR1_WIDTH_0, `ETH_IPGR1_DEF_0) IPGR1_0 | |
470 | ( | |
471 | .DataIn (DataIn[`ETH_IPGR1_WIDTH_0 - 1:0]), | |
472 | .DataOut (IPGR1Out[`ETH_IPGR1_WIDTH_0 - 1:0]), | |
473 | .Write (IPGR1_Wr[0]), | |
474 | .Clk (Clk), | |
475 | .Reset (Reset), | |
476 | .SyncReset (1'b0) | |
477 | ); | |
478 | assign IPGR1Out[31:`ETH_IPGR1_WIDTH_0] = 0; | |
479 | ||
480 | // IPGR2 Register | |
481 | eth_register #(`ETH_IPGR2_WIDTH_0, `ETH_IPGR2_DEF_0) IPGR2_0 | |
482 | ( | |
483 | .DataIn (DataIn[`ETH_IPGR2_WIDTH_0 - 1:0]), | |
484 | .DataOut (IPGR2Out[`ETH_IPGR2_WIDTH_0 - 1:0]), | |
485 | .Write (IPGR2_Wr[0]), | |
486 | .Clk (Clk), | |
487 | .Reset (Reset), | |
488 | .SyncReset (1'b0) | |
489 | ); | |
490 | assign IPGR2Out[31:`ETH_IPGR2_WIDTH_0] = 0; | |
491 | ||
492 | // PACKETLEN Register | |
493 | eth_register #(`ETH_PACKETLEN_WIDTH_0, `ETH_PACKETLEN_DEF_0) PACKETLEN_0 | |
494 | ( | |
495 | .DataIn (DataIn[`ETH_PACKETLEN_WIDTH_0 - 1:0]), | |
496 | .DataOut (PACKETLENOut[`ETH_PACKETLEN_WIDTH_0 - 1:0]), | |
497 | .Write (PACKETLEN_Wr[0]), | |
498 | .Clk (Clk), | |
499 | .Reset (Reset), | |
500 | .SyncReset (1'b0) | |
501 | ); | |
502 | eth_register #(`ETH_PACKETLEN_WIDTH_1, `ETH_PACKETLEN_DEF_1) PACKETLEN_1 | |
503 | ( | |
504 | .DataIn (DataIn[`ETH_PACKETLEN_WIDTH_1 + 7:8]), | |
505 | .DataOut (PACKETLENOut[`ETH_PACKETLEN_WIDTH_1 + 7:8]), | |
506 | .Write (PACKETLEN_Wr[1]), | |
507 | .Clk (Clk), | |
508 | .Reset (Reset), | |
509 | .SyncReset (1'b0) | |
510 | ); | |
511 | eth_register #(`ETH_PACKETLEN_WIDTH_2, `ETH_PACKETLEN_DEF_2) PACKETLEN_2 | |
512 | ( | |
513 | .DataIn (DataIn[`ETH_PACKETLEN_WIDTH_2 + 15:16]), | |
514 | .DataOut (PACKETLENOut[`ETH_PACKETLEN_WIDTH_2 + 15:16]), | |
515 | .Write (PACKETLEN_Wr[2]), | |
516 | .Clk (Clk), | |
517 | .Reset (Reset), | |
518 | .SyncReset (1'b0) | |
519 | ); | |
520 | eth_register #(`ETH_PACKETLEN_WIDTH_3, `ETH_PACKETLEN_DEF_3) PACKETLEN_3 | |
521 | ( | |
522 | .DataIn (DataIn[`ETH_PACKETLEN_WIDTH_3 + 23:24]), | |
523 | .DataOut (PACKETLENOut[`ETH_PACKETLEN_WIDTH_3 + 23:24]), | |
524 | .Write (PACKETLEN_Wr[3]), | |
525 | .Clk (Clk), | |
526 | .Reset (Reset), | |
527 | .SyncReset (1'b0) | |
528 | ); | |
529 | ||
530 | // COLLCONF Register | |
531 | eth_register #(`ETH_COLLCONF_WIDTH_0, `ETH_COLLCONF_DEF_0) COLLCONF_0 | |
532 | ( | |
533 | .DataIn (DataIn[`ETH_COLLCONF_WIDTH_0 - 1:0]), | |
534 | .DataOut (COLLCONFOut[`ETH_COLLCONF_WIDTH_0 - 1:0]), | |
535 | .Write (COLLCONF_Wr[0]), | |
536 | .Clk (Clk), | |
537 | .Reset (Reset), | |
538 | .SyncReset (1'b0) | |
539 | ); | |
540 | eth_register #(`ETH_COLLCONF_WIDTH_2, `ETH_COLLCONF_DEF_2) COLLCONF_2 | |
541 | ( | |
542 | .DataIn (DataIn[`ETH_COLLCONF_WIDTH_2 + 15:16]), | |
543 | .DataOut (COLLCONFOut[`ETH_COLLCONF_WIDTH_2 + 15:16]), | |
544 | .Write (COLLCONF_Wr[2]), | |
545 | .Clk (Clk), | |
546 | .Reset (Reset), | |
547 | .SyncReset (1'b0) | |
548 | ); | |
549 | assign COLLCONFOut[15:`ETH_COLLCONF_WIDTH_0] = 0; | |
550 | assign COLLCONFOut[31:`ETH_COLLCONF_WIDTH_2 + 16] = 0; | |
551 | ||
552 | // TX_BD_NUM Register | |
553 | eth_register #(`ETH_TX_BD_NUM_WIDTH_0, `ETH_TX_BD_NUM_DEF_0) TX_BD_NUM_0 | |
554 | ( | |
555 | .DataIn (DataIn[`ETH_TX_BD_NUM_WIDTH_0 - 1:0]), | |
556 | .DataOut (TX_BD_NUMOut[`ETH_TX_BD_NUM_WIDTH_0 - 1:0]), | |
557 | .Write (TX_BD_NUM_Wr[0]), | |
558 | .Clk (Clk), | |
559 | .Reset (Reset), | |
560 | .SyncReset (1'b0) | |
561 | ); | |
562 | assign TX_BD_NUMOut[31:`ETH_TX_BD_NUM_WIDTH_0] = 0; | |
563 | ||
564 | // CTRLMODER Register | |
565 | eth_register #(`ETH_CTRLMODER_WIDTH_0, `ETH_CTRLMODER_DEF_0) CTRLMODER_0 | |
566 | ( | |
567 | .DataIn (DataIn[`ETH_CTRLMODER_WIDTH_0 - 1:0]), | |
568 | .DataOut (CTRLMODEROut[`ETH_CTRLMODER_WIDTH_0 - 1:0]), | |
569 | .Write (CTRLMODER_Wr[0]), | |
570 | .Clk (Clk), | |
571 | .Reset (Reset), | |
572 | .SyncReset (1'b0) | |
573 | ); | |
574 | assign CTRLMODEROut[31:`ETH_CTRLMODER_WIDTH_0] = 0; | |
575 | ||
576 | // MIIMODER Register | |
577 | eth_register #(`ETH_MIIMODER_WIDTH_0, `ETH_MIIMODER_DEF_0) MIIMODER_0 | |
578 | ( | |
579 | .DataIn (DataIn[`ETH_MIIMODER_WIDTH_0 - 1:0]), | |
580 | .DataOut (MIIMODEROut[`ETH_MIIMODER_WIDTH_0 - 1:0]), | |
581 | .Write (MIIMODER_Wr[0]), | |
582 | .Clk (Clk), | |
583 | .Reset (Reset), | |
584 | .SyncReset (1'b0) | |
585 | ); | |
586 | eth_register #(`ETH_MIIMODER_WIDTH_1, `ETH_MIIMODER_DEF_1) MIIMODER_1 | |
587 | ( | |
588 | .DataIn (DataIn[`ETH_MIIMODER_WIDTH_1 + 7:8]), | |
589 | .DataOut (MIIMODEROut[`ETH_MIIMODER_WIDTH_1 + 7:8]), | |
590 | .Write (MIIMODER_Wr[1]), | |
591 | .Clk (Clk), | |
592 | .Reset (Reset), | |
593 | .SyncReset (1'b0) | |
594 | ); | |
595 | assign MIIMODEROut[31:`ETH_MIIMODER_WIDTH_1 + 8] = 0; | |
596 | ||
597 | // MIICOMMAND Register | |
598 | eth_register #(1, 0) MIICOMMAND0 | |
599 | ( | |
600 | .DataIn (DataIn[0]), | |
601 | .DataOut (MIICOMMANDOut[0]), | |
602 | .Write (MIICOMMAND_Wr[0]), | |
603 | .Clk (Clk), | |
604 | .Reset (Reset), | |
605 | .SyncReset (1'b0) | |
606 | ); | |
607 | eth_register #(1, 0) MIICOMMAND1 | |
608 | ( | |
609 | .DataIn (DataIn[1]), | |
610 | .DataOut (MIICOMMANDOut[1]), | |
611 | .Write (MIICOMMAND_Wr[0]), | |
612 | .Clk (Clk), | |
613 | .Reset (Reset), | |
614 | .SyncReset (RStatStart) | |
615 | ); | |
616 | eth_register #(1, 0) MIICOMMAND2 | |
617 | ( | |
618 | .DataIn (DataIn[2]), | |
619 | .DataOut (MIICOMMANDOut[2]), | |
620 | .Write (MIICOMMAND_Wr[0]), | |
621 | .Clk (Clk), | |
622 | .Reset (Reset), | |
623 | .SyncReset (WCtrlDataStart) | |
624 | ); | |
625 | assign MIICOMMANDOut[31:`ETH_MIICOMMAND_WIDTH_0] = 29'h0; | |
626 | ||
627 | // MIIADDRESSRegister | |
628 | eth_register #(`ETH_MIIADDRESS_WIDTH_0, `ETH_MIIADDRESS_DEF_0) MIIADDRESS_0 | |
629 | ( | |
630 | .DataIn (DataIn[`ETH_MIIADDRESS_WIDTH_0 - 1:0]), | |
631 | .DataOut (MIIADDRESSOut[`ETH_MIIADDRESS_WIDTH_0 - 1:0]), | |
632 | .Write (MIIADDRESS_Wr[0]), | |
633 | .Clk (Clk), | |
634 | .Reset (Reset), | |
635 | .SyncReset (1'b0) | |
636 | ); | |
637 | eth_register #(`ETH_MIIADDRESS_WIDTH_1, `ETH_MIIADDRESS_DEF_1) MIIADDRESS_1 | |
638 | ( | |
639 | .DataIn (DataIn[`ETH_MIIADDRESS_WIDTH_1 + 7:8]), | |
640 | .DataOut (MIIADDRESSOut[`ETH_MIIADDRESS_WIDTH_1 + 7:8]), | |
641 | .Write (MIIADDRESS_Wr[1]), | |
642 | .Clk (Clk), | |
643 | .Reset (Reset), | |
644 | .SyncReset (1'b0) | |
645 | ); | |
646 | assign MIIADDRESSOut[7:`ETH_MIIADDRESS_WIDTH_0] = 0; | |
647 | assign MIIADDRESSOut[31:`ETH_MIIADDRESS_WIDTH_1 + 8] = 0; | |
648 | ||
649 | // MIITX_DATA Register | |
650 | eth_register #(`ETH_MIITX_DATA_WIDTH_0, `ETH_MIITX_DATA_DEF_0) MIITX_DATA_0 | |
651 | ( | |
652 | .DataIn (DataIn[`ETH_MIITX_DATA_WIDTH_0 - 1:0]), | |
653 | .DataOut (MIITX_DATAOut[`ETH_MIITX_DATA_WIDTH_0 - 1:0]), | |
654 | .Write (MIITX_DATA_Wr[0]), | |
655 | .Clk (Clk), | |
656 | .Reset (Reset), | |
657 | .SyncReset (1'b0) | |
658 | ); | |
659 | eth_register #(`ETH_MIITX_DATA_WIDTH_1, `ETH_MIITX_DATA_DEF_1) MIITX_DATA_1 | |
660 | ( | |
661 | .DataIn (DataIn[`ETH_MIITX_DATA_WIDTH_1 + 7:8]), | |
662 | .DataOut (MIITX_DATAOut[`ETH_MIITX_DATA_WIDTH_1 + 7:8]), | |
663 | .Write (MIITX_DATA_Wr[1]), | |
664 | .Clk (Clk), | |
665 | .Reset (Reset), | |
666 | .SyncReset (1'b0) | |
667 | ); | |
668 | assign MIITX_DATAOut[31:`ETH_MIITX_DATA_WIDTH_1 + 8] = 0; | |
669 | ||
670 | // MIIRX_DATA Register | |
671 | eth_register #(`ETH_MIIRX_DATA_WIDTH, `ETH_MIIRX_DATA_DEF) MIIRX_DATA | |
672 | ( | |
673 | .DataIn (Prsd[`ETH_MIIRX_DATA_WIDTH-1:0]), | |
674 | .DataOut (MIIRX_DATAOut[`ETH_MIIRX_DATA_WIDTH-1:0]), | |
675 | .Write (MIIRX_DATA_Wr), // not written from WB | |
676 | .Clk (Clk), | |
677 | .Reset (Reset), | |
678 | .SyncReset (1'b0) | |
679 | ); | |
680 | assign MIIRX_DATAOut[31:`ETH_MIIRX_DATA_WIDTH] = 0; | |
681 | ||
682 | // MAC_ADDR0 Register | |
683 | eth_register #(`ETH_MAC_ADDR0_WIDTH_0, `ETH_MAC_ADDR0_DEF_0) MAC_ADDR0_0 | |
684 | ( | |
685 | .DataIn (DataIn[`ETH_MAC_ADDR0_WIDTH_0 - 1:0]), | |
686 | .DataOut (MAC_ADDR0Out[`ETH_MAC_ADDR0_WIDTH_0 - 1:0]), | |
687 | .Write (MAC_ADDR0_Wr[0]), | |
688 | .Clk (Clk), | |
689 | .Reset (Reset), | |
690 | .SyncReset (1'b0) | |
691 | ); | |
692 | eth_register #(`ETH_MAC_ADDR0_WIDTH_1, `ETH_MAC_ADDR0_DEF_1) MAC_ADDR0_1 | |
693 | ( | |
694 | .DataIn (DataIn[`ETH_MAC_ADDR0_WIDTH_1 + 7:8]), | |
695 | .DataOut (MAC_ADDR0Out[`ETH_MAC_ADDR0_WIDTH_1 + 7:8]), | |
696 | .Write (MAC_ADDR0_Wr[1]), | |
697 | .Clk (Clk), | |
698 | .Reset (Reset), | |
699 | .SyncReset (1'b0) | |
700 | ); | |
701 | eth_register #(`ETH_MAC_ADDR0_WIDTH_2, `ETH_MAC_ADDR0_DEF_2) MAC_ADDR0_2 | |
702 | ( | |
703 | .DataIn (DataIn[`ETH_MAC_ADDR0_WIDTH_2 + 15:16]), | |
704 | .DataOut (MAC_ADDR0Out[`ETH_MAC_ADDR0_WIDTH_2 + 15:16]), | |
705 | .Write (MAC_ADDR0_Wr[2]), | |
706 | .Clk (Clk), | |
707 | .Reset (Reset), | |
708 | .SyncReset (1'b0) | |
709 | ); | |
710 | eth_register #(`ETH_MAC_ADDR0_WIDTH_3, `ETH_MAC_ADDR0_DEF_3) MAC_ADDR0_3 | |
711 | ( | |
712 | .DataIn (DataIn[`ETH_MAC_ADDR0_WIDTH_3 + 23:24]), | |
713 | .DataOut (MAC_ADDR0Out[`ETH_MAC_ADDR0_WIDTH_3 + 23:24]), | |
714 | .Write (MAC_ADDR0_Wr[3]), | |
715 | .Clk (Clk), | |
716 | .Reset (Reset), | |
717 | .SyncReset (1'b0) | |
718 | ); | |
719 | ||
720 | // MAC_ADDR1 Register | |
721 | eth_register #(`ETH_MAC_ADDR1_WIDTH_0, `ETH_MAC_ADDR1_DEF_0) MAC_ADDR1_0 | |
722 | ( | |
723 | .DataIn (DataIn[`ETH_MAC_ADDR1_WIDTH_0 - 1:0]), | |
724 | .DataOut (MAC_ADDR1Out[`ETH_MAC_ADDR1_WIDTH_0 - 1:0]), | |
725 | .Write (MAC_ADDR1_Wr[0]), | |
726 | .Clk (Clk), | |
727 | .Reset (Reset), | |
728 | .SyncReset (1'b0) | |
729 | ); | |
730 | eth_register #(`ETH_MAC_ADDR1_WIDTH_1, `ETH_MAC_ADDR1_DEF_1) MAC_ADDR1_1 | |
731 | ( | |
732 | .DataIn (DataIn[`ETH_MAC_ADDR1_WIDTH_1 + 7:8]), | |
733 | .DataOut (MAC_ADDR1Out[`ETH_MAC_ADDR1_WIDTH_1 + 7:8]), | |
734 | .Write (MAC_ADDR1_Wr[1]), | |
735 | .Clk (Clk), | |
736 | .Reset (Reset), | |
737 | .SyncReset (1'b0) | |
738 | ); | |
739 | assign MAC_ADDR1Out[31:`ETH_MAC_ADDR1_WIDTH_1 + 8] = 0; | |
740 | ||
741 | // RXHASH0 Register | |
742 | eth_register #(`ETH_HASH0_WIDTH_0, `ETH_HASH0_DEF_0) RXHASH0_0 | |
743 | ( | |
744 | .DataIn (DataIn[`ETH_HASH0_WIDTH_0 - 1:0]), | |
745 | .DataOut (HASH0Out[`ETH_HASH0_WIDTH_0 - 1:0]), | |
746 | .Write (HASH0_Wr[0]), | |
747 | .Clk (Clk), | |
748 | .Reset (Reset), | |
749 | .SyncReset (1'b0) | |
750 | ); | |
751 | eth_register #(`ETH_HASH0_WIDTH_1, `ETH_HASH0_DEF_1) RXHASH0_1 | |
752 | ( | |
753 | .DataIn (DataIn[`ETH_HASH0_WIDTH_1 + 7:8]), | |
754 | .DataOut (HASH0Out[`ETH_HASH0_WIDTH_1 + 7:8]), | |
755 | .Write (HASH0_Wr[1]), | |
756 | .Clk (Clk), | |
757 | .Reset (Reset), | |
758 | .SyncReset (1'b0) | |
759 | ); | |
760 | eth_register #(`ETH_HASH0_WIDTH_2, `ETH_HASH0_DEF_2) RXHASH0_2 | |
761 | ( | |
762 | .DataIn (DataIn[`ETH_HASH0_WIDTH_2 + 15:16]), | |
763 | .DataOut (HASH0Out[`ETH_HASH0_WIDTH_2 + 15:16]), | |
764 | .Write (HASH0_Wr[2]), | |
765 | .Clk (Clk), | |
766 | .Reset (Reset), | |
767 | .SyncReset (1'b0) | |
768 | ); | |
769 | eth_register #(`ETH_HASH0_WIDTH_3, `ETH_HASH0_DEF_3) RXHASH0_3 | |
770 | ( | |
771 | .DataIn (DataIn[`ETH_HASH0_WIDTH_3 + 23:24]), | |
772 | .DataOut (HASH0Out[`ETH_HASH0_WIDTH_3 + 23:24]), | |
773 | .Write (HASH0_Wr[3]), | |
774 | .Clk (Clk), | |
775 | .Reset (Reset), | |
776 | .SyncReset (1'b0) | |
777 | ); | |
778 | ||
779 | // RXHASH1 Register | |
780 | eth_register #(`ETH_HASH1_WIDTH_0, `ETH_HASH1_DEF_0) RXHASH1_0 | |
781 | ( | |
782 | .DataIn (DataIn[`ETH_HASH1_WIDTH_0 - 1:0]), | |
783 | .DataOut (HASH1Out[`ETH_HASH1_WIDTH_0 - 1:0]), | |
784 | .Write (HASH1_Wr[0]), | |
785 | .Clk (Clk), | |
786 | .Reset (Reset), | |
787 | .SyncReset (1'b0) | |
788 | ); | |
789 | eth_register #(`ETH_HASH1_WIDTH_1, `ETH_HASH1_DEF_1) RXHASH1_1 | |
790 | ( | |
791 | .DataIn (DataIn[`ETH_HASH1_WIDTH_1 + 7:8]), | |
792 | .DataOut (HASH1Out[`ETH_HASH1_WIDTH_1 + 7:8]), | |
793 | .Write (HASH1_Wr[1]), | |
794 | .Clk (Clk), | |
795 | .Reset (Reset), | |
796 | .SyncReset (1'b0) | |
797 | ); | |
798 | eth_register #(`ETH_HASH1_WIDTH_2, `ETH_HASH1_DEF_2) RXHASH1_2 | |
799 | ( | |
800 | .DataIn (DataIn[`ETH_HASH1_WIDTH_2 + 15:16]), | |
801 | .DataOut (HASH1Out[`ETH_HASH1_WIDTH_2 + 15:16]), | |
802 | .Write (HASH1_Wr[2]), | |
803 | .Clk (Clk), | |
804 | .Reset (Reset), | |
805 | .SyncReset (1'b0) | |
806 | ); | |
807 | eth_register #(`ETH_HASH1_WIDTH_3, `ETH_HASH1_DEF_3) RXHASH1_3 | |
808 | ( | |
809 | .DataIn (DataIn[`ETH_HASH1_WIDTH_3 + 23:24]), | |
810 | .DataOut (HASH1Out[`ETH_HASH1_WIDTH_3 + 23:24]), | |
811 | .Write (HASH1_Wr[3]), | |
812 | .Clk (Clk), | |
813 | .Reset (Reset), | |
814 | .SyncReset (1'b0) | |
815 | ); | |
816 | ||
817 | // TXCTRL Register | |
818 | eth_register #(`ETH_TX_CTRL_WIDTH_0, `ETH_TX_CTRL_DEF_0) TXCTRL_0 | |
819 | ( | |
820 | .DataIn (DataIn[`ETH_TX_CTRL_WIDTH_0 - 1:0]), | |
821 | .DataOut (TXCTRLOut[`ETH_TX_CTRL_WIDTH_0 - 1:0]), | |
822 | .Write (TXCTRL_Wr[0]), | |
823 | .Clk (Clk), | |
824 | .Reset (Reset), | |
825 | .SyncReset (1'b0) | |
826 | ); | |
827 | eth_register #(`ETH_TX_CTRL_WIDTH_1, `ETH_TX_CTRL_DEF_1) TXCTRL_1 | |
828 | ( | |
829 | .DataIn (DataIn[`ETH_TX_CTRL_WIDTH_1 + 7:8]), | |
830 | .DataOut (TXCTRLOut[`ETH_TX_CTRL_WIDTH_1 + 7:8]), | |
831 | .Write (TXCTRL_Wr[1]), | |
832 | .Clk (Clk), | |
833 | .Reset (Reset), | |
834 | .SyncReset (1'b0) | |
835 | ); | |
836 | eth_register #(`ETH_TX_CTRL_WIDTH_2, `ETH_TX_CTRL_DEF_2) TXCTRL_2 // Request bit is synchronously reset | |
837 | ( | |
838 | .DataIn (DataIn[`ETH_TX_CTRL_WIDTH_2 + 15:16]), | |
839 | .DataOut (TXCTRLOut[`ETH_TX_CTRL_WIDTH_2 + 15:16]), | |
840 | .Write (TXCTRL_Wr[2]), | |
841 | .Clk (Clk), | |
842 | .Reset (Reset), | |
843 | .SyncReset (RstTxPauseRq) | |
844 | ); | |
845 | assign TXCTRLOut[31:`ETH_TX_CTRL_WIDTH_2 + 16] = 0; | |
846 | ||
847 | ||
848 | ||
849 | // Reading data from registers | |
850 | always @ (Address or Read or MODEROut or INT_SOURCEOut or | |
851 | INT_MASKOut or IPGTOut or IPGR1Out or IPGR2Out or | |
852 | PACKETLENOut or COLLCONFOut or CTRLMODEROut or MIIMODEROut or | |
853 | MIICOMMANDOut or MIIADDRESSOut or MIITX_DATAOut or MIIRX_DATAOut or | |
854 | MIISTATUSOut or MAC_ADDR0Out or MAC_ADDR1Out or TX_BD_NUMOut or | |
855 | HASH0Out or HASH1Out or TXCTRLOut | |
856 | ) | |
857 | begin | |
858 | if(Read) // read | |
859 | begin | |
860 | case(Address) | |
861 | `ETH_MODER_ADR : DataOut<=MODEROut; | |
862 | `ETH_INT_SOURCE_ADR : DataOut<=INT_SOURCEOut; | |
863 | `ETH_INT_MASK_ADR : DataOut<=INT_MASKOut; | |
864 | `ETH_IPGT_ADR : DataOut<=IPGTOut; | |
865 | `ETH_IPGR1_ADR : DataOut<=IPGR1Out; | |
866 | `ETH_IPGR2_ADR : DataOut<=IPGR2Out; | |
867 | `ETH_PACKETLEN_ADR : DataOut<=PACKETLENOut; | |
868 | `ETH_COLLCONF_ADR : DataOut<=COLLCONFOut; | |
869 | `ETH_CTRLMODER_ADR : DataOut<=CTRLMODEROut; | |
870 | `ETH_MIIMODER_ADR : DataOut<=MIIMODEROut; | |
871 | `ETH_MIICOMMAND_ADR : DataOut<=MIICOMMANDOut; | |
872 | `ETH_MIIADDRESS_ADR : DataOut<=MIIADDRESSOut; | |
873 | `ETH_MIITX_DATA_ADR : DataOut<=MIITX_DATAOut; | |
874 | `ETH_MIIRX_DATA_ADR : DataOut<=MIIRX_DATAOut; | |
875 | `ETH_MIISTATUS_ADR : DataOut<=MIISTATUSOut; | |
876 | `ETH_MAC_ADDR0_ADR : DataOut<=MAC_ADDR0Out; | |
877 | `ETH_MAC_ADDR1_ADR : DataOut<=MAC_ADDR1Out; | |
878 | `ETH_TX_BD_NUM_ADR : DataOut<=TX_BD_NUMOut; | |
879 | `ETH_HASH0_ADR : DataOut<=HASH0Out; | |
880 | `ETH_HASH1_ADR : DataOut<=HASH1Out; | |
881 | `ETH_TX_CTRL_ADR : DataOut<=TXCTRLOut; | |
882 | ||
883 | default: DataOut<=32'h0; | |
884 | endcase | |
885 | end | |
886 | else | |
887 | DataOut<=32'h0; | |
888 | end | |
889 | ||
890 | ||
891 | assign r_RecSmall = MODEROut[16]; | |
892 | assign r_Pad = MODEROut[15]; | |
893 | assign r_HugEn = MODEROut[14]; | |
894 | assign r_CrcEn = MODEROut[13]; | |
895 | assign r_DlyCrcEn = MODEROut[12]; | |
896 | // assign r_Rst = MODEROut[11]; This signal is not used any more | |
897 | assign r_FullD = MODEROut[10]; | |
898 | assign r_ExDfrEn = MODEROut[9]; | |
899 | assign r_NoBckof = MODEROut[8]; | |
900 | assign r_LoopBck = MODEROut[7]; | |
901 | assign r_IFG = MODEROut[6]; | |
902 | assign r_Pro = MODEROut[5]; | |
903 | assign r_Iam = MODEROut[4]; | |
904 | assign r_Bro = MODEROut[3]; | |
905 | assign r_NoPre = MODEROut[2]; | |
906 | assign r_TxEn = MODEROut[1] & (TX_BD_NUMOut>0); // Transmission is enabled when there is at least one TxBD. | |
907 | assign r_RxEn = MODEROut[0] & (TX_BD_NUMOut<'h80); // Reception is enabled when there is at least one RxBD. | |
908 | ||
909 | assign r_IPGT[6:0] = IPGTOut[6:0]; | |
910 | ||
911 | assign r_IPGR1[6:0] = IPGR1Out[6:0]; | |
912 | ||
913 | assign r_IPGR2[6:0] = IPGR2Out[6:0]; | |
914 | ||
915 | assign r_MinFL[15:0] = PACKETLENOut[31:16]; | |
916 | assign r_MaxFL[15:0] = PACKETLENOut[15:0]; | |
917 | ||
918 | assign r_MaxRet[3:0] = COLLCONFOut[19:16]; | |
919 | assign r_CollValid[5:0] = COLLCONFOut[5:0]; | |
920 | ||
921 | assign r_TxFlow = CTRLMODEROut[2]; | |
922 | assign r_RxFlow = CTRLMODEROut[1]; | |
923 | assign r_PassAll = CTRLMODEROut[0]; | |
924 | ||
925 | assign r_MiiNoPre = MIIMODEROut[8]; | |
926 | assign r_ClkDiv[7:0] = MIIMODEROut[7:0]; | |
927 | ||
928 | assign r_WCtrlData = MIICOMMANDOut[2]; | |
929 | assign r_RStat = MIICOMMANDOut[1]; | |
930 | assign r_ScanStat = MIICOMMANDOut[0]; | |
931 | ||
932 | assign r_RGAD[4:0] = MIIADDRESSOut[12:8]; | |
933 | assign r_FIAD[4:0] = MIIADDRESSOut[4:0]; | |
934 | ||
935 | assign r_CtrlData[15:0] = MIITX_DATAOut[15:0]; | |
936 | ||
937 | assign MIISTATUSOut[31:`ETH_MIISTATUS_WIDTH] = 0; | |
938 | assign MIISTATUSOut[2] = NValid_stat ; | |
939 | assign MIISTATUSOut[1] = Busy_stat ; | |
940 | assign MIISTATUSOut[0] = LinkFail ; | |
941 | ||
942 | assign r_MAC[31:0] = MAC_ADDR0Out[31:0]; | |
943 | assign r_MAC[47:32] = MAC_ADDR1Out[15:0]; | |
944 | assign r_HASH1[31:0] = HASH1Out; | |
945 | assign r_HASH0[31:0] = HASH0Out; | |
946 | ||
947 | assign r_TxBDNum[7:0] = TX_BD_NUMOut[7:0]; | |
948 | ||
949 | assign r_TxPauseTV[15:0] = TXCTRLOut[15:0]; | |
950 | assign r_TxPauseRq = TXCTRLOut[16]; | |
951 | ||
952 | ||
953 | // Synchronizing TxC Interrupt | |
954 | always @ (posedge TxClk or posedge Reset) | |
955 | begin | |
956 | if(Reset) | |
957 | SetTxCIrq_txclk <=#Tp 1'b0; | |
958 | else | |
959 | if(TxCtrlEndFrm & StartTxDone & r_TxFlow) | |
960 | SetTxCIrq_txclk <=#Tp 1'b1; | |
961 | else | |
962 | if(ResetTxCIrq_sync2) | |
963 | SetTxCIrq_txclk <=#Tp 1'b0; | |
964 | end | |
965 | ||
966 | ||
967 | always @ (posedge Clk or posedge Reset) | |
968 | begin | |
969 | if(Reset) | |
970 | SetTxCIrq_sync1 <=#Tp 1'b0; | |
971 | else | |
972 | SetTxCIrq_sync1 <=#Tp SetTxCIrq_txclk; | |
973 | end | |
974 | ||
975 | always @ (posedge Clk or posedge Reset) | |
976 | begin | |
977 | if(Reset) | |
978 | SetTxCIrq_sync2 <=#Tp 1'b0; | |
979 | else | |
980 | SetTxCIrq_sync2 <=#Tp SetTxCIrq_sync1; | |
981 | end | |
982 | ||
983 | always @ (posedge Clk or posedge Reset) | |
984 | begin | |
985 | if(Reset) | |
986 | SetTxCIrq_sync3 <=#Tp 1'b0; | |
987 | else | |
988 | SetTxCIrq_sync3 <=#Tp SetTxCIrq_sync2; | |
989 | end | |
990 | ||
991 | always @ (posedge Clk or posedge Reset) | |
992 | begin | |
993 | if(Reset) | |
994 | SetTxCIrq <=#Tp 1'b0; | |
995 | else | |
996 | SetTxCIrq <=#Tp SetTxCIrq_sync2 & ~SetTxCIrq_sync3; | |
997 | end | |
998 | ||
999 | always @ (posedge TxClk or posedge Reset) | |
1000 | begin | |
1001 | if(Reset) | |
1002 | ResetTxCIrq_sync1 <=#Tp 1'b0; | |
1003 | else | |
1004 | ResetTxCIrq_sync1 <=#Tp SetTxCIrq_sync2; | |
1005 | end | |
1006 | ||
1007 | always @ (posedge TxClk or posedge Reset) | |
1008 | begin | |
1009 | if(Reset) | |
1010 | ResetTxCIrq_sync2 <=#Tp 1'b0; | |
1011 | else | |
1012 | ResetTxCIrq_sync2 <=#Tp SetTxCIrq_sync1; | |
1013 | end | |
1014 | ||
1015 | ||
1016 | // Synchronizing RxC Interrupt | |
1017 | always @ (posedge RxClk or posedge Reset) | |
1018 | begin | |
1019 | if(Reset) | |
1020 | SetRxCIrq_rxclk <=#Tp 1'b0; | |
1021 | else | |
1022 | if(SetPauseTimer & r_RxFlow) | |
1023 | SetRxCIrq_rxclk <=#Tp 1'b1; | |
1024 | else | |
1025 | if(ResetRxCIrq_sync2 & (~ResetRxCIrq_sync3)) | |
1026 | SetRxCIrq_rxclk <=#Tp 1'b0; | |
1027 | end | |
1028 | ||
1029 | ||
1030 | always @ (posedge Clk or posedge Reset) | |
1031 | begin | |
1032 | if(Reset) | |
1033 | SetRxCIrq_sync1 <=#Tp 1'b0; | |
1034 | else | |
1035 | SetRxCIrq_sync1 <=#Tp SetRxCIrq_rxclk; | |
1036 | end | |
1037 | ||
1038 | always @ (posedge Clk or posedge Reset) | |
1039 | begin | |
1040 | if(Reset) | |
1041 | SetRxCIrq_sync2 <=#Tp 1'b0; | |
1042 | else | |
1043 | SetRxCIrq_sync2 <=#Tp SetRxCIrq_sync1; | |
1044 | end | |
1045 | ||
1046 | always @ (posedge Clk or posedge Reset) | |
1047 | begin | |
1048 | if(Reset) | |
1049 | SetRxCIrq_sync3 <=#Tp 1'b0; | |
1050 | else | |
1051 | SetRxCIrq_sync3 <=#Tp SetRxCIrq_sync2; | |
1052 | end | |
1053 | ||
1054 | always @ (posedge Clk or posedge Reset) | |
1055 | begin | |
1056 | if(Reset) | |
1057 | SetRxCIrq <=#Tp 1'b0; | |
1058 | else | |
1059 | SetRxCIrq <=#Tp SetRxCIrq_sync2 & ~SetRxCIrq_sync3; | |
1060 | end | |
1061 | ||
1062 | always @ (posedge RxClk or posedge Reset) | |
1063 | begin | |
1064 | if(Reset) | |
1065 | ResetRxCIrq_sync1 <=#Tp 1'b0; | |
1066 | else | |
1067 | ResetRxCIrq_sync1 <=#Tp SetRxCIrq_sync2; | |
1068 | end | |
1069 | ||
1070 | always @ (posedge RxClk or posedge Reset) | |
1071 | begin | |
1072 | if(Reset) | |
1073 | ResetRxCIrq_sync2 <=#Tp 1'b0; | |
1074 | else | |
1075 | ResetRxCIrq_sync2 <=#Tp ResetRxCIrq_sync1; | |
1076 | end | |
1077 | ||
1078 | always @ (posedge RxClk or posedge Reset) | |
1079 | begin | |
1080 | if(Reset) | |
1081 | ResetRxCIrq_sync3 <=#Tp 1'b0; | |
1082 | else | |
1083 | ResetRxCIrq_sync3 <=#Tp ResetRxCIrq_sync2; | |
1084 | end | |
1085 | ||
1086 | ||
1087 | ||
1088 | // Interrupt generation | |
1089 | always @ (posedge Clk or posedge Reset) | |
1090 | begin | |
1091 | if(Reset) | |
1092 | irq_txb <= 1'b0; | |
1093 | else | |
1094 | if(TxB_IRQ) | |
1095 | irq_txb <= #Tp 1'b1; | |
1096 | else | |
1097 | if(INT_SOURCE_Wr[0] & DataIn[0]) | |
1098 | irq_txb <= #Tp 1'b0; | |
1099 | end | |
1100 | ||
1101 | always @ (posedge Clk or posedge Reset) | |
1102 | begin | |
1103 | if(Reset) | |
1104 | irq_txe <= 1'b0; | |
1105 | else | |
1106 | if(TxE_IRQ) | |
1107 | irq_txe <= #Tp 1'b1; | |
1108 | else | |
1109 | if(INT_SOURCE_Wr[0] & DataIn[1]) | |
1110 | irq_txe <= #Tp 1'b0; | |
1111 | end | |
1112 | ||
1113 | always @ (posedge Clk or posedge Reset) | |
1114 | begin | |
1115 | if(Reset) | |
1116 | irq_rxb <= 1'b0; | |
1117 | else | |
1118 | if(RxB_IRQ) | |
1119 | irq_rxb <= #Tp 1'b1; | |
1120 | else | |
1121 | if(INT_SOURCE_Wr[0] & DataIn[2]) | |
1122 | irq_rxb <= #Tp 1'b0; | |
1123 | end | |
1124 | ||
1125 | always @ (posedge Clk or posedge Reset) | |
1126 | begin | |
1127 | if(Reset) | |
1128 | irq_rxe <= 1'b0; | |
1129 | else | |
1130 | if(RxE_IRQ) | |
1131 | irq_rxe <= #Tp 1'b1; | |
1132 | else | |
1133 | if(INT_SOURCE_Wr[0] & DataIn[3]) | |
1134 | irq_rxe <= #Tp 1'b0; | |
1135 | end | |
1136 | ||
1137 | always @ (posedge Clk or posedge Reset) | |
1138 | begin | |
1139 | if(Reset) | |
1140 | irq_busy <= 1'b0; | |
1141 | else | |
1142 | if(Busy_IRQ) | |
1143 | irq_busy <= #Tp 1'b1; | |
1144 | else | |
1145 | if(INT_SOURCE_Wr[0] & DataIn[4]) | |
1146 | irq_busy <= #Tp 1'b0; | |
1147 | end | |
1148 | ||
1149 | always @ (posedge Clk or posedge Reset) | |
1150 | begin | |
1151 | if(Reset) | |
1152 | irq_txc <= 1'b0; | |
1153 | else | |
1154 | if(SetTxCIrq) | |
1155 | irq_txc <= #Tp 1'b1; | |
1156 | else | |
1157 | if(INT_SOURCE_Wr[0] & DataIn[5]) | |
1158 | irq_txc <= #Tp 1'b0; | |
1159 | end | |
1160 | ||
1161 | always @ (posedge Clk or posedge Reset) | |
1162 | begin | |
1163 | if(Reset) | |
1164 | irq_rxc <= 1'b0; | |
1165 | else | |
1166 | if(SetRxCIrq) | |
1167 | irq_rxc <= #Tp 1'b1; | |
1168 | else | |
1169 | if(INT_SOURCE_Wr[0] & DataIn[6]) | |
1170 | irq_rxc <= #Tp 1'b0; | |
1171 | end | |
1172 | ||
1173 | // Generating interrupt signal | |
1174 | assign int_o = irq_txb & INT_MASKOut[0] | | |
1175 | irq_txe & INT_MASKOut[1] | | |
1176 | irq_rxb & INT_MASKOut[2] | | |
1177 | irq_rxe & INT_MASKOut[3] | | |
1178 | irq_busy & INT_MASKOut[4] | | |
1179 | irq_txc & INT_MASKOut[5] | | |
1180 | irq_rxc & INT_MASKOut[6] ; | |
1181 | ||
1182 | // For reading interrupt status | |
1183 | assign INT_SOURCEOut = {{(32-`ETH_INT_SOURCE_WIDTH_0){1'b0}}, irq_rxc, irq_txc, irq_busy, irq_rxe, irq_rxb, irq_txe, irq_txb}; | |
1184 | ||
1185 | ||
1186 | ||
1187 | endmodule |