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1 | ////////////////////////////////////////////////////////////////////// | |
2 | //// //// | |
3 | //// File name: pci_conf_space.v //// | |
4 | //// //// | |
5 | //// This file is part of the "PCI bridge" project //// | |
6 | //// http://www.opencores.org/cores/pci/ //// | |
7 | //// //// | |
8 | //// Author(s): //// | |
9 | //// - tadej@opencores.org //// | |
10 | //// - Tadej Markovic //// | |
11 | //// //// | |
12 | //// All additional information is avaliable in the README.txt //// | |
13 | //// file. //// | |
14 | //// //// | |
15 | //// //// | |
16 | ////////////////////////////////////////////////////////////////////// | |
17 | //// //// | |
18 | //// Copyright (C) 2000 Tadej Markovic, tadej@opencores.org //// | |
19 | //// //// | |
20 | //// This source file may be used and distributed without //// | |
21 | //// restriction provided that this copyright statement is not //// | |
22 | //// removed from the file and that any derivative work contains //// | |
23 | //// the original copyright notice and the associated disclaimer. //// | |
24 | //// //// | |
25 | //// This source file is free software; you can redistribute it //// | |
26 | //// and/or modify it under the terms of the GNU Lesser General //// | |
27 | //// Public License as published by the Free Software Foundation; //// | |
28 | //// either version 2.1 of the License, or (at your option) any //// | |
29 | //// later version. //// | |
30 | //// //// | |
31 | //// This source is distributed in the hope that it will be //// | |
32 | //// useful, but WITHOUT ANY WARRANTY; without even the implied //// | |
33 | //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// | |
34 | //// PURPOSE. See the GNU Lesser General Public License for more //// | |
35 | //// details. //// | |
36 | //// //// | |
37 | //// You should have received a copy of the GNU Lesser General //// | |
38 | //// Public License along with this source; if not, download it //// | |
39 | //// from http://www.opencores.org/lgpl.shtml //// | |
40 | //// //// | |
41 | ////////////////////////////////////////////////////////////////////// | |
42 | // | |
43 | // CVS Revision History | |
44 | // | |
45 | // $Log: pci_conf_space.v,v $ | |
46 | // Revision 1.1 2007-03-20 17:50:56 sithglan | |
47 | // add shit | |
48 | // | |
49 | // Revision 1.10 2004/08/19 16:04:53 mihad | |
50 | // Removed some unused signals. | |
51 | // | |
52 | // Revision 1.9 2004/08/19 15:27:34 mihad | |
53 | // Changed minimum pci image size to 256 bytes because | |
54 | // of some PC system problems with size of IO images. | |
55 | // | |
56 | // Revision 1.8 2004/07/07 12:45:01 mihad | |
57 | // Added SubsystemVendorID, SubsystemID, MAXLatency, MinGnt defines. | |
58 | // Enabled value loading from serial EEPROM for all of the above + VendorID and DeviceID registers. | |
59 | // | |
60 | // Revision 1.7 2004/01/24 11:54:18 mihad | |
61 | // Update! SPOCI Implemented! | |
62 | // | |
63 | // Revision 1.6 2003/12/28 09:54:48 fr2201 | |
64 | // def_wb_imagex_addr_map defined correctly | |
65 | // | |
66 | // Revision 1.5 2003/12/28 09:20:00 fr2201 | |
67 | // Reset values for PCI, WB defined (PCI_TAx,WB_BAx,WB_TAx,WB_AMx,WB_BAx_MEM_IO) | |
68 | // | |
69 | // Revision 1.4 2003/12/19 11:11:30 mihad | |
70 | // Compact PCI Hot Swap support added. | |
71 | // New testcases added. | |
72 | // Specification updated. | |
73 | // Test application changed to support WB B3 cycles. | |
74 | // | |
75 | // Revision 1.3 2003/08/14 13:06:02 simons | |
76 | // synchronizer_flop replaced with pci_synchronizer_flop, artisan ram instance updated. | |
77 | // | |
78 | // Revision 1.2 2003/03/26 13:16:18 mihad | |
79 | // Added the reset value parameter to the synchronizer flop module. | |
80 | // Added resets to all synchronizer flop instances. | |
81 | // Repaired initial sync value in fifos. | |
82 | // | |
83 | // Revision 1.1 2003/01/27 16:49:31 mihad | |
84 | // Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed. | |
85 | // | |
86 | // Revision 1.4 2002/08/13 11:03:53 mihad | |
87 | // Added a few testcases. Repaired wrong reset value for PCI_AM5 register. Repaired Parity Error Detected bit setting. Changed PCI_AM0 to always enabled(regardles of PCI_AM0 define), if image 0 is used as configuration image | |
88 | // | |
89 | // Revision 1.3 2002/02/01 15:25:12 mihad | |
90 | // Repaired a few bugs, updated specification, added test bench files and design document | |
91 | // | |
92 | // Revision 1.2 2001/10/05 08:14:28 mihad | |
93 | // Updated all files with inclusion of timescale file for simulation purposes. | |
94 | // | |
95 | // Revision 1.1.1.1 2001/10/02 15:33:46 mihad | |
96 | // New project directory structure | |
97 | // | |
98 | // | |
99 | ||
100 | `include "pci_constants.v" | |
101 | ||
102 | // synopsys translate_off | |
103 | `include "timescale.v" | |
104 | // synopsys translate_on | |
105 | ||
106 | /*----------------------------------------------------------------------------------------------------------- | |
107 | w_ prefix is a sign for Write (and read) side of Dual-Port registers | |
108 | r_ prefix is a sign for Read only side of Dual-Port registers | |
109 | In the first line there are DATA and ADDRESS ports, in the second line there are write enable and read | |
110 | enable signals with chip-select (conf_hit) for config. space. | |
111 | In the third line there are output signlas from Command register of the PCI configuration header !!! | |
112 | In the fourth line there are input signals to Status register of the PCI configuration header !!! | |
113 | In the fifth line there is output from Latency Timer & r_Interrupt pin registers of the PCI conf. header !!! | |
114 | Following are IMAGE specific registers, from which PCI_BASE_ADDR registers are the same as base address | |
115 | registers from the PCI conf. header !!! | |
116 | -----------------------------------------------------------------------------------------------------------*/ | |
117 | // normal R/W address, data and control | |
118 | module pci_conf_space | |
119 | ( w_conf_address_in, w_conf_data_in, w_conf_data_out, r_conf_address_in, r_conf_data_out, | |
120 | w_we_i, w_re, r_re, w_byte_en_in, w_clock, reset, pci_clk, wb_clk, | |
121 | // outputs from command register of the PCI header | |
122 | serr_enable, perr_response, pci_master_enable, memory_space_enable, io_space_enable, | |
123 | // inputs to status register of the PCI header | |
124 | perr_in, serr_in, master_abort_recv, target_abort_recv, target_abort_set, master_data_par_err, | |
125 | // output from cache_line_size, latency timer and r_interrupt_pin register of the PCI header | |
126 | cache_line_size_to_pci, cache_line_size_to_wb, cache_lsize_not_zero_to_wb, | |
127 | latency_tim, | |
128 | // output from all pci IMAGE registers | |
129 | pci_base_addr0, pci_base_addr1, pci_base_addr2, pci_base_addr3, pci_base_addr4, pci_base_addr5, | |
130 | pci_memory_io0, pci_memory_io1, pci_memory_io2, pci_memory_io3, pci_memory_io4, pci_memory_io5, | |
131 | pci_addr_mask0, pci_addr_mask1, pci_addr_mask2, pci_addr_mask3, pci_addr_mask4, pci_addr_mask5, | |
132 | pci_tran_addr0, pci_tran_addr1, pci_tran_addr2, pci_tran_addr3, pci_tran_addr4, pci_tran_addr5, | |
133 | pci_img_ctrl0, pci_img_ctrl1, pci_img_ctrl2, pci_img_ctrl3, pci_img_ctrl4, pci_img_ctrl5, | |
134 | // input to pci error control and status register, error address and error data registers | |
135 | pci_error_be, pci_error_bc, pci_error_rty_exp, pci_error_es, pci_error_sig, pci_error_addr, | |
136 | pci_error_data, | |
137 | // output from all wishbone IMAGE registers | |
138 | wb_base_addr0, wb_base_addr1, wb_base_addr2, wb_base_addr3, wb_base_addr4, wb_base_addr5, | |
139 | wb_memory_io0, wb_memory_io1, wb_memory_io2, wb_memory_io3, wb_memory_io4, wb_memory_io5, | |
140 | wb_addr_mask0, wb_addr_mask1, wb_addr_mask2, wb_addr_mask3, wb_addr_mask4, wb_addr_mask5, | |
141 | wb_tran_addr0, wb_tran_addr1, wb_tran_addr2, wb_tran_addr3, wb_tran_addr4, wb_tran_addr5, | |
142 | wb_img_ctrl0, wb_img_ctrl1, wb_img_ctrl2, wb_img_ctrl3, wb_img_ctrl4, wb_img_ctrl5, | |
143 | // input to wb error control and status register, error address and error data registers | |
144 | wb_error_be, wb_error_bc, wb_error_rty_exp, wb_error_es, wb_error_sig, wb_error_addr, wb_error_data, | |
145 | // output from conf. cycle generation register (sddress), int. control register & interrupt output | |
146 | config_addr, icr_soft_res, int_out, | |
147 | // input to interrupt status register | |
148 | isr_sys_err_int, isr_par_err_int, isr_int_prop, | |
149 | ||
150 | pci_init_complete_out, wb_init_complete_out | |
151 | ||
152 | `ifdef PCI_CPCI_HS_IMPLEMENT | |
153 | , | |
154 | pci_cpci_hs_enum_oe_o, pci_cpci_hs_led_oe_o, pci_cpci_hs_es_i | |
155 | `endif | |
156 | ||
157 | `ifdef PCI_SPOCI | |
158 | , | |
159 | spoci_scl_oe_o, spoci_sda_i, spoci_sda_oe_o | |
160 | `endif | |
161 | ) ; | |
162 | ||
163 | ||
164 | /*########################################################################################################### | |
165 | ///////////////////////////////////////////////////////////////////////////////////////////////////////////// | |
166 | Input and output ports | |
167 | ====================== | |
168 | ///////////////////////////////////////////////////////////////////////////////////////////////////////////// | |
169 | ###########################################################################################################*/ | |
170 | ||
171 | // output data | |
172 | output [31 : 0] w_conf_data_out ; | |
173 | output [31 : 0] r_conf_data_out ; | |
174 | reg [31 : 0] w_conf_data_out ; | |
175 | ||
176 | `ifdef NO_CNF_IMAGE | |
177 | `else | |
178 | reg [31 : 0] r_conf_data_out ; | |
179 | `endif | |
180 | ||
181 | // input data | |
182 | input [31 : 0] w_conf_data_in ; | |
183 | wire [31 : 0] w_conf_pdata_reduced ; // reduced data written into PCI image registers | |
184 | wire [31 : 0] w_conf_wdata_reduced ; // reduced data written into WB image registers | |
185 | // input address | |
186 | input [11 : 0] w_conf_address_in ; | |
187 | input [11 : 0] r_conf_address_in ; | |
188 | // input control signals | |
189 | input w_we_i ; | |
190 | input w_re ; | |
191 | input r_re ; | |
192 | input [3 : 0] w_byte_en_in ; | |
193 | input w_clock ; | |
194 | input reset ; | |
195 | input pci_clk ; | |
196 | input wb_clk ; | |
197 | // PCI header outputs from command register | |
198 | output serr_enable ; | |
199 | output perr_response ; | |
200 | output pci_master_enable ; | |
201 | output memory_space_enable ; | |
202 | output io_space_enable ; | |
203 | // PCI header inputs to status register | |
204 | input perr_in ; | |
205 | input serr_in ; | |
206 | input master_abort_recv ; | |
207 | input target_abort_recv ; | |
208 | input target_abort_set ; | |
209 | input master_data_par_err ; | |
210 | // PCI header output from cache_line_size, latency timer and interrupt pin | |
211 | output [7 : 0] cache_line_size_to_pci ; // sinchronized to PCI clock | |
212 | output [7 : 0] cache_line_size_to_wb ; // sinchronized to WB clock | |
213 | output cache_lsize_not_zero_to_wb ; // used in WBU and PCIU | |
214 | output [7 : 0] latency_tim ; | |
215 | //output [2 : 0] int_pin ; // only 3 LSbits are important! | |
216 | // PCI output from image registers | |
217 | `ifdef GUEST | |
218 | output [31:12] pci_base_addr0 ; | |
219 | `endif | |
220 | ||
221 | `ifdef HOST | |
222 | `ifdef NO_CNF_IMAGE | |
223 | output [31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] pci_base_addr0 ; | |
224 | `else | |
225 | output [31:12] pci_base_addr0 ; | |
226 | `endif | |
227 | `endif | |
228 | ||
229 | output [31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] pci_base_addr1 ; | |
230 | output [31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] pci_base_addr2 ; | |
231 | output [31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] pci_base_addr3 ; | |
232 | output [31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] pci_base_addr4 ; | |
233 | output [31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] pci_base_addr5 ; | |
234 | output pci_memory_io0 ; | |
235 | output pci_memory_io1 ; | |
236 | output pci_memory_io2 ; | |
237 | output pci_memory_io3 ; | |
238 | output pci_memory_io4 ; | |
239 | output pci_memory_io5 ; | |
240 | output [31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] pci_addr_mask0 ; | |
241 | output [31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] pci_addr_mask1 ; | |
242 | output [31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] pci_addr_mask2 ; | |
243 | output [31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] pci_addr_mask3 ; | |
244 | output [31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] pci_addr_mask4 ; | |
245 | output [31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] pci_addr_mask5 ; | |
246 | output [31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] pci_tran_addr0 ; | |
247 | output [31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] pci_tran_addr1 ; | |
248 | output [31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] pci_tran_addr2 ; | |
249 | output [31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] pci_tran_addr3 ; | |
250 | output [31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] pci_tran_addr4 ; | |
251 | output [31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] pci_tran_addr5 ; | |
252 | output [2 : 1] pci_img_ctrl0 ; | |
253 | output [2 : 1] pci_img_ctrl1 ; | |
254 | output [2 : 1] pci_img_ctrl2 ; | |
255 | output [2 : 1] pci_img_ctrl3 ; | |
256 | output [2 : 1] pci_img_ctrl4 ; | |
257 | output [2 : 1] pci_img_ctrl5 ; | |
258 | // PCI input to pci error control and status register, error address and error data registers | |
259 | input [3 : 0] pci_error_be ; | |
260 | input [3 : 0] pci_error_bc ; | |
261 | input pci_error_rty_exp ; | |
262 | input pci_error_es ; | |
263 | input pci_error_sig ; | |
264 | input [31 : 0] pci_error_addr ; | |
265 | input [31 : 0] pci_error_data ; | |
266 | // WISHBONE output from image registers | |
267 | output [31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] wb_base_addr0 ; | |
268 | output [31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] wb_base_addr1 ; | |
269 | output [31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] wb_base_addr2 ; | |
270 | output [31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] wb_base_addr3 ; | |
271 | output [31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] wb_base_addr4 ; | |
272 | output [31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] wb_base_addr5 ; | |
273 | output wb_memory_io0 ; | |
274 | output wb_memory_io1 ; | |
275 | output wb_memory_io2 ; | |
276 | output wb_memory_io3 ; | |
277 | output wb_memory_io4 ; | |
278 | output wb_memory_io5 ; | |
279 | output [31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] wb_addr_mask0 ; | |
280 | output [31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] wb_addr_mask1 ; | |
281 | output [31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] wb_addr_mask2 ; | |
282 | output [31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] wb_addr_mask3 ; | |
283 | output [31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] wb_addr_mask4 ; | |
284 | output [31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] wb_addr_mask5 ; | |
285 | output [31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] wb_tran_addr0 ; | |
286 | output [31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] wb_tran_addr1 ; | |
287 | output [31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] wb_tran_addr2 ; | |
288 | output [31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] wb_tran_addr3 ; | |
289 | output [31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] wb_tran_addr4 ; | |
290 | output [31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] wb_tran_addr5 ; | |
291 | output [2 : 0] wb_img_ctrl0 ; | |
292 | output [2 : 0] wb_img_ctrl1 ; | |
293 | output [2 : 0] wb_img_ctrl2 ; | |
294 | output [2 : 0] wb_img_ctrl3 ; | |
295 | output [2 : 0] wb_img_ctrl4 ; | |
296 | output [2 : 0] wb_img_ctrl5 ; | |
297 | // WISHBONE input to wb error control and status register, error address and error data registers | |
298 | input [3 : 0] wb_error_be ; | |
299 | input [3 : 0] wb_error_bc ; | |
300 | input wb_error_rty_exp ; | |
301 | input wb_error_es ; | |
302 | input wb_error_sig ; | |
303 | input [31 : 0] wb_error_addr ; | |
304 | input [31 : 0] wb_error_data ; | |
305 | // GENERAL output from conf. cycle generation register & int. control register | |
306 | output [23 : 0] config_addr ; | |
307 | output icr_soft_res ; | |
308 | output int_out ; | |
309 | // GENERAL input to interrupt status register | |
310 | input isr_sys_err_int ; | |
311 | input isr_par_err_int ; | |
312 | input isr_int_prop ; | |
313 | ||
314 | output pci_init_complete_out ; | |
315 | output wb_init_complete_out ; | |
316 | ||
317 | `ifdef PCI_CPCI_HS_IMPLEMENT | |
318 | output pci_cpci_hs_enum_oe_o ; | |
319 | output pci_cpci_hs_led_oe_o ; | |
320 | input pci_cpci_hs_es_i ; | |
321 | ||
322 | reg pci_cpci_hs_enum_oe_o ; | |
323 | reg pci_cpci_hs_led_oe_o ; | |
324 | ||
325 | // set the hot swap ejector switch debounce counter width | |
326 | // it is only 4 for simulation purposes | |
327 | `ifdef PCI_CPCI_SIM | |
328 | ||
329 | parameter hs_es_cnt_width = 4 ; | |
330 | ||
331 | `else | |
332 | ||
333 | `ifdef PCI33 | |
334 | ||
335 | parameter hs_es_cnt_width = 16 ; | |
336 | ||
337 | `endif | |
338 | ||
339 | `ifdef PCI66 | |
340 | ||
341 | parameter hs_es_cnt_width = 17 ; | |
342 | ||
343 | `endif | |
344 | `endif | |
345 | ||
346 | `endif | |
347 | ||
348 | `ifdef PCI_SPOCI | |
349 | output spoci_scl_oe_o ; | |
350 | input spoci_sda_i ; | |
351 | output spoci_sda_oe_o ; | |
352 | ||
353 | reg spoci_cs_nack, | |
354 | spoci_cs_write, | |
355 | spoci_cs_read; | |
356 | ||
357 | reg [10: 0] spoci_cs_adr ; | |
358 | reg [ 7: 0] spoci_cs_dat ; | |
359 | `endif | |
360 | ||
361 | /*########################################################################################################### | |
362 | ///////////////////////////////////////////////////////////////////////////////////////////////////////////// | |
363 | REGISTERS definition | |
364 | ==================== | |
365 | ///////////////////////////////////////////////////////////////////////////////////////////////////////////// | |
366 | ###########################################################################################################*/ | |
367 | ||
368 | // Decoded Register Select signals for writting (only one address decoder) | |
369 | reg [56 : 0] w_reg_select_dec ; | |
370 | ||
371 | /*########################################################################################################### | |
372 | ------------------------------------------------------------------------------------------------------------- | |
373 | PCI CONFIGURATION SPACE HEADER (type 00h) registers | |
374 | ||
375 | BIST and some other registers are not implemented and therefor written in correct | |
376 | place with comment line. There are also some registers with NOT all bits implemented and therefor uses | |
377 | _bitX or _bitX2_X1 to sign which bit or range of bits are implemented. | |
378 | Some special cases and examples are described below! | |
379 | ------------------------------------------------------------------------------------------------------------- | |
380 | ###########################################################################################################*/ | |
381 | ||
382 | /*----------------------------------------------------------------------------------------------------------- | |
383 | [000h-00Ch] First 4 DWORDs (32-bit) of PCI configuration header - the same regardless of the HEADER type ! | |
384 | r_ prefix is a sign for read only registers | |
385 | Vendor_ID is an ID for a specific vendor defined by PCI_SIG - 2321h does not belong to anyone (e.g. | |
386 | Xilinx's Vendor_ID is 10EEh and Altera's Vendor_ID is 1172h). Device_ID and Revision_ID should be used | |
387 | together by application. Class_Code has 3 bytes to define BASE class (06h for PCI Bridge), SUB class | |
388 | (00h for HOST type, 80h for Other Bridge type) and Interface type (00h for normal). | |
389 | -----------------------------------------------------------------------------------------------------------*/ | |
390 | reg [15: 0] r_vendor_id ; | |
391 | reg [15: 0] r_device_id ; | |
392 | reg [15: 0] r_subsys_vendor_id ; | |
393 | reg [15: 0] r_subsys_id ; | |
394 | ||
395 | reg command_bit8 ; | |
396 | reg command_bit6 ; | |
397 | reg [2 : 0] command_bit2_0 ; | |
398 | reg [15 : 11] status_bit15_11 ; | |
399 | parameter r_status_bit10_9 = 2'b01 ; // 2'b01 means MEDIUM devsel timing !!! | |
400 | reg status_bit8 ; | |
401 | parameter r_status_bit7 = 1'b1 ; // fast back-to-back capable response !!! | |
402 | parameter r_status_bit5 = `HEADER_66MHz ; // 1'b0 indicates 33 MHz capable !!! | |
403 | ||
404 | `ifdef PCI_CPCI_HS_IMPLEMENT | |
405 | wire r_status_bit4 = 1 ; | |
406 | reg hs_ins ; | |
407 | reg hs_ext ; | |
408 | wire [ 1: 0] hs_pi = 2'b00 ; | |
409 | reg hs_loo ; | |
410 | reg hs_eim ; | |
411 | wire [ 7: 0] hs_cap_id = 8'h06 ; | |
412 | reg hs_ins_armed ; | |
413 | reg hs_ext_armed ; | |
414 | `else | |
415 | wire r_status_bit4 = 0 ; | |
416 | `endif | |
417 | ||
418 | reg [ 7: 0] r_revision_id ; | |
419 | ||
420 | `ifdef HOST | |
421 | parameter r_class_code = 24'h06_00_00 ; | |
422 | `else | |
423 | parameter r_class_code = 24'h06_80_00 ; | |
424 | `endif | |
425 | reg [7 : 0] cache_line_size_reg ; | |
426 | reg [7 : 0] latency_timer ; | |
427 | parameter r_header_type = 8'h00 ; | |
428 | // REG bist NOT implemented !!! | |
429 | ||
430 | /*----------------------------------------------------------------------------------------------------------- | |
431 | [010h-03Ch] all other DWORDs (32-bit) of PCI configuration header - only for HEADER type 00h ! | |
432 | r_ prefix is a sign for read only registers | |
433 | BASE_ADDRESS_REGISTERS are the same as ones in the PCI Target configuration registers section. They | |
434 | are duplicated and therefor defined just ones and used with the same name as written below. If | |
435 | IMAGEx is NOT defined there is only parameter image_X assigned to '0' and this parameter is used | |
436 | elsewhere in the code. This parameter is defined in the INTERNAL SIGNALS part !!! | |
437 | Interrupt_Pin value 8'h01 is used for INT_A pin used. | |
438 | MIN_GNT and MAX_LAT are used for device's desired values for Latency Timer value. The value in boath | |
439 | registers specifies a period of time in units of 1/4 microsecond. ZERO indicates that there are no | |
440 | major requirements for the settings of Latency Timer. | |
441 | MIN_GNT specifieshow how long a burst period the device needs at 33MHz. MAX_LAT specifies how often | |
442 | the device needs to gain access to the PCI bus. Values are choosen assuming that the target does not | |
443 | insert any wait states. Follow the expamle of settings for simple display card. | |
444 | If we use 64 (32-bit) FIFO locations for one burst then we need 8 x 1/4 microsecond periods at 33MHz | |
445 | clock rate => MIN_GNT = 08h ! Resolution is 1024 x 768 (= 786432 pixels for one frame) with 16-bit | |
446 | color mode. We can transfere 2 16-bit pixels in one FIFO location. From that we calculate, that for | |
447 | one frame we need 6144 burst transferes in 1/25 second. So we need one burst every 6,51 microsecond | |
448 | and that is 26 x 1/4 microsecond or 1Ah x 1/4 microsecond => MAX_LAT = 1Ah ! | |
449 | -----------------------------------------------------------------------------------------------------------*/ | |
450 | // REG x 6 base_address_register_X IMPLEMENTED as pci_ba_X !!! | |
451 | // REG r_cardbus_cis_pointer NOT implemented !!! | |
452 | // REG r_subsystem_vendor_id NOT implemented !!! | |
453 | // REG r_subsystem_id NOT implemented !!! | |
454 | // REG r_expansion_rom_base_address NOT implemented !!! | |
455 | // REG r_cap_list_pointer NOT implemented !!! | |
456 | reg [7 : 0] interrupt_line ; | |
457 | parameter r_interrupt_pin = 8'h01 ; | |
458 | reg [7 : 0] r_min_gnt ; | |
459 | reg [7 : 0] r_max_lat ; | |
460 | ||
461 | /*########################################################################################################### | |
462 | ------------------------------------------------------------------------------------------------------------- | |
463 | PCI Target configuration registers | |
464 | There are also some registers with NOT all bits implemented and therefor uses _bitX or _bitX2_X1 to | |
465 | sign which bit or range of bits are implemented. Some special cases and examples are described below! | |
466 | ------------------------------------------------------------------------------------------------------------- | |
467 | ###########################################################################################################*/ | |
468 | ||
469 | /*----------------------------------------------------------------------------------------------------------- | |
470 | [100h-168h] | |
471 | Depending on defines (PCI_IMAGE1 or .. or PCI_IMAGE5 or (PCI_IMAGE0 and HOST)) in constants.v file, | |
472 | there are registers corresponding to each IMAGE defined to REG and parameter pci_image_X assigned to '1'. | |
473 | The maximum number of images is "6". By default there are first two images used and the first (PCI_IMAGE0) | |
474 | is assigned to Configuration space! With a 'define' PCI_IMAGEx you choose the number of used PCI IMAGES | |
475 | in a bridge without PCI_IMAGE0 (e.g. PCI_IMAGE3 tells, that PCI_IMAGE1, PCI_IMAGE2 and PCI_IMAGE3 are | |
476 | used for mapping the space from WB to PCI. Offcourse, PCI_IMAGE0 is assigned to Configuration space). | |
477 | That leave us PCI_IMAGE5 as the maximum number of images. | |
478 | There is one exeption, when the core is implemented as HOST. If so, then the PCI specification allowes | |
479 | the Configuration space NOT to be visible on the PCI bus. With `define PCI_IMAGE0 (and `define HOST), we | |
480 | assign PCI_IMAGE0 to normal WB to PCI image and not to configuration space! | |
481 | ||
482 | When error occurs, PCI ERR_ADDR and ERR_DATA registers stores address and data on the bus that | |
483 | caused error. While ERR_CS register stores Byte Enables and Bus Command in the MSByte. In bits 10 | |
484 | and 8 it reports Retry Counter Expired (for posted writes), Error Source (Master Abort) and Error | |
485 | Report Signal (signals that error has occured) respectively. With bit 0 we enable Error Reporting | |
486 | mechanism. | |
487 | -----------------------------------------------------------------------------------------------------------*/ | |
488 | `ifdef HOST | |
489 | `ifdef NO_CNF_IMAGE | |
490 | `ifdef PCI_IMAGE0 // if PCI bridge is HOST and IMAGE0 is assigned as general image space | |
491 | reg [31 : 8] pci_ba0_bit31_8 ; | |
492 | reg [2 : 1] pci_img_ctrl0_bit2_1 ; | |
493 | reg pci_ba0_bit0 ; | |
494 | reg [31 : 8] pci_am0 ; | |
495 | reg [31 : 8] pci_ta0 ; | |
496 | `else // if PCI bridge is HOST and IMAGE0 is not used | |
497 | wire [31 : 8] pci_ba0_bit31_8 = 24'h0000_00 ; // NO base address needed | |
498 | wire [2 : 1] pci_img_ctrl0_bit2_1 = 2'b00 ; // NO addr.transl. and pre-fetch | |
499 | wire pci_ba0_bit0 = 0 ; // config. space is MEMORY space | |
500 | wire [31 : 8] pci_am0 = 24'h0000_00 ; // NO address mask needed | |
501 | wire [31 : 8] pci_ta0 = 24'h0000_00 ; // NO address translation needed | |
502 | `endif | |
503 | `else // if PCI bridge is HOST and IMAGE0 is assigned to PCI configuration space | |
504 | reg [31 : 8] pci_ba0_bit31_8 ; | |
505 | wire [2 : 1] pci_img_ctrl0_bit2_1 = 2'b00 ; // NO pre-fetch and read line support | |
506 | wire pci_ba0_bit0 = 0 ; // config. space is MEMORY space | |
507 | wire [31 : 8] pci_am0 = 24'hFFFF_F0 ; // address mask for configuration image always 20'hffff_f | |
508 | wire [31 : 8] pci_ta0 = 24'h0000_00 ; // NO address translation needed | |
509 | `endif | |
510 | `endif | |
511 | ||
512 | `ifdef GUEST // if PCI bridge is GUEST, then IMAGE0 is assigned to PCI configuration space | |
513 | reg [31 : 8] pci_ba0_bit31_8 ; | |
514 | wire [2 : 1] pci_img_ctrl0_bit2_1 = 2'b00 ; // NO addr.transl. and pre-fetch | |
515 | wire pci_ba0_bit0 = 0 ; // config. space is MEMORY space | |
516 | wire [31 : 8] pci_am0 = 24'hffff_f0 ; // address mask for configuration image always 24'hffff_f0 - 4KB mem image | |
517 | wire [31 : 8] pci_ta0 = 24'h0000_00 ; // NO address translation needed | |
518 | `endif | |
519 | ||
520 | // IMAGE1 is included by default, meanwhile other IMAGEs are optional !!! | |
521 | reg [2 : 1] pci_img_ctrl1_bit2_1 ; | |
522 | reg [31 : 8] pci_ba1_bit31_8 ; | |
523 | `ifdef HOST | |
524 | reg pci_ba1_bit0 ; | |
525 | `else | |
526 | wire pci_ba1_bit0 = `PCI_BA1_MEM_IO ; | |
527 | `endif | |
528 | reg [31 : 8] pci_am1 ; | |
529 | reg [31 : 8] pci_ta1 ; | |
530 | `ifdef PCI_IMAGE2 | |
531 | reg [2 : 1] pci_img_ctrl2_bit2_1 ; | |
532 | reg [31 : 8] pci_ba2_bit31_8 ; | |
533 | `ifdef HOST | |
534 | reg pci_ba2_bit0 ; | |
535 | `else | |
536 | wire pci_ba2_bit0 = `PCI_BA2_MEM_IO ; | |
537 | `endif | |
538 | reg [31 : 8] pci_am2 ; | |
539 | reg [31 : 8] pci_ta2 ; | |
540 | `else | |
541 | wire [2 : 1] pci_img_ctrl2_bit2_1 = 2'b00 ; | |
542 | wire [31 : 8] pci_ba2_bit31_8 = 24'h0000_00 ; | |
543 | wire pci_ba2_bit0 = 1'b0 ; | |
544 | wire [31 : 8] pci_am2 = 24'h0000_00 ; | |
545 | wire [31 : 8] pci_ta2 = 24'h0000_00 ; | |
546 | `endif | |
547 | `ifdef PCI_IMAGE3 | |
548 | reg [2 : 1] pci_img_ctrl3_bit2_1 ; | |
549 | reg [31 : 8] pci_ba3_bit31_8 ; | |
550 | `ifdef HOST | |
551 | reg pci_ba3_bit0 ; | |
552 | `else | |
553 | wire pci_ba3_bit0 = `PCI_BA3_MEM_IO ; | |
554 | `endif | |
555 | reg [31 : 8] pci_am3 ; | |
556 | reg [31 : 8] pci_ta3 ; | |
557 | `else | |
558 | wire [2 : 1] pci_img_ctrl3_bit2_1 = 2'b00 ; | |
559 | wire [31 : 8] pci_ba3_bit31_8 = 24'h0000_00 ; | |
560 | wire pci_ba3_bit0 = 1'b0 ; | |
561 | wire [31 : 8] pci_am3 = 24'h0000_00 ; | |
562 | wire [31 : 8] pci_ta3 = 24'h0000_00 ; | |
563 | `endif | |
564 | `ifdef PCI_IMAGE4 | |
565 | reg [2 : 1] pci_img_ctrl4_bit2_1 ; | |
566 | reg [31 : 8] pci_ba4_bit31_8 ; | |
567 | `ifdef HOST | |
568 | reg pci_ba4_bit0 ; | |
569 | `else | |
570 | wire pci_ba4_bit0 = `PCI_BA4_MEM_IO ; | |
571 | `endif | |
572 | reg [31 : 8] pci_am4 ; | |
573 | reg [31 : 8] pci_ta4 ; | |
574 | `else | |
575 | wire [2 : 1] pci_img_ctrl4_bit2_1 = 2'b00 ; | |
576 | wire [31 : 8] pci_ba4_bit31_8 = 24'h0000_00 ; | |
577 | wire pci_ba4_bit0 = 1'b0 ; | |
578 | wire [31 : 8] pci_am4 = 24'h0000_00 ; | |
579 | wire [31 : 8] pci_ta4 = 24'h0000_00 ; | |
580 | `endif | |
581 | `ifdef PCI_IMAGE5 | |
582 | reg [2 : 1] pci_img_ctrl5_bit2_1 ; | |
583 | reg [31 : 8] pci_ba5_bit31_8 ; | |
584 | `ifdef HOST | |
585 | reg pci_ba5_bit0 ; | |
586 | `else | |
587 | wire pci_ba5_bit0 = `PCI_BA5_MEM_IO ; | |
588 | `endif | |
589 | reg [31 : 8] pci_am5 ; | |
590 | reg [31 : 8] pci_ta5 ; | |
591 | `else | |
592 | wire [2 : 1] pci_img_ctrl5_bit2_1 = 2'b00 ; | |
593 | wire [31 : 8] pci_ba5_bit31_8 = 24'h0000_00 ; | |
594 | wire pci_ba5_bit0 = 1'b0 ; | |
595 | wire [31 : 8] pci_am5 = 24'h0000_00 ; | |
596 | wire [31 : 8] pci_ta5 = 24'h0000_00 ; | |
597 | `endif | |
598 | reg [31 : 24] pci_err_cs_bit31_24 ; | |
599 | reg pci_err_cs_bit10 ; | |
600 | reg pci_err_cs_bit9 ; | |
601 | reg pci_err_cs_bit8 ; | |
602 | reg pci_err_cs_bit0 ; | |
603 | reg [31 : 0] pci_err_addr ; | |
604 | reg [31 : 0] pci_err_data ; | |
605 | ||
606 | ||
607 | /*########################################################################################################### | |
608 | ------------------------------------------------------------------------------------------------------------- | |
609 | WISHBONE Slave configuration registers | |
610 | There are also some registers with NOT all bits implemented and therefor uses _bitX or _bitX2_X1 to | |
611 | sign which bit or range of bits are implemented. Some special cases and examples are described below! | |
612 | ------------------------------------------------------------------------------------------------------------- | |
613 | ###########################################################################################################*/ | |
614 | ||
615 | /*----------------------------------------------------------------------------------------------------------- | |
616 | [800h-85Ch] | |
617 | Depending on defines (WB_IMAGE1 or .. or WB_IMAGE4 or WB_IMAGE5) in constants.v file, there are | |
618 | registers corresponding to each IMAGE defined to REG and parameter wb_image_X assigned to '1'. | |
619 | The maximum number of images is "6". By default there are first two images used and the first (WB_IMAGE0) | |
620 | is assigned to Configuration space! With a 'define' WB_IMAGEx you choose the number of used WB IMAGES in | |
621 | a bridge without WB_IMAGE0 (e.g. WB_IMAGE3 tells, that WB_IMAGE1, WB_IMAGE2 and WB_IMAGE3 are used for | |
622 | mapping the space from PCI to WB. Offcourse, WB_IMAGE0 is assigned to Configuration space). That leave | |
623 | us WB_IMAGE5 as the maximum number of images. | |
624 | ||
625 | When error occurs, WISHBONE ERR_ADDR and ERR_DATA registers stores address and data on the bus that | |
626 | caused error. While ERR_CS register stores Byte Enables and Bus Command in the MSByte. In bits 10, 9 | |
627 | and 8 it reports Retry Counter Expired (for posted writes), Error Source (Master Abort) and Error | |
628 | Report Signal (signals that error has occured) respectively. With bit 0 we enable Error Reporting | |
629 | mechanism. | |
630 | -----------------------------------------------------------------------------------------------------------*/ | |
631 | // WB_IMAGE0 is always assigned to config. space or is not used | |
632 | wire [2 : 0] wb_img_ctrl0_bit2_0 = 3'b000 ; // NO addr.transl., pre-fetch and read-line | |
633 | wire [31 : 12] wb_ba0_bit31_12 = `WB_CONFIGURATION_BASE ; | |
634 | wire wb_ba0_bit0 = 0 ; // config. space is MEMORY space | |
635 | wire [31 : 12] wb_am0 = `WB_AM0 ; // 4KBytes of configuration space is minimum | |
636 | wire [31 : 12] wb_ta0 = 20'h0000_0 ; // NO address translation needed | |
637 | // WB_IMAGE1 is included by default meanwhile others are optional ! | |
638 | reg [2 : 0] wb_img_ctrl1_bit2_0 ; | |
639 | reg [31 : 12] wb_ba1_bit31_12 ; | |
640 | reg wb_ba1_bit0 ; | |
641 | reg [31 : 12] wb_am1 ; | |
642 | reg [31 : 12] wb_ta1 ; | |
643 | `ifdef WB_IMAGE2 | |
644 | reg [2 : 0] wb_img_ctrl2_bit2_0 ; | |
645 | reg [31 : 12] wb_ba2_bit31_12 ; | |
646 | reg wb_ba2_bit0 ; | |
647 | reg [31 : 12] wb_am2 ; | |
648 | reg [31 : 12] wb_ta2 ; | |
649 | `else | |
650 | wire [2 : 0] wb_img_ctrl2_bit2_0 = 3'b000 ; | |
651 | wire [31 : 12] wb_ba2_bit31_12 = 20'h0000_0 ; | |
652 | wire wb_ba2_bit0 = 1'b0 ; | |
653 | wire [31 : 12] wb_am2 = 20'h0000_0 ; | |
654 | wire [31 : 12] wb_ta2 = 20'h0000_0 ; | |
655 | `endif | |
656 | `ifdef WB_IMAGE3 | |
657 | reg [2 : 0] wb_img_ctrl3_bit2_0 ; | |
658 | reg [31 : 12] wb_ba3_bit31_12 ; | |
659 | reg wb_ba3_bit0 ; | |
660 | reg [31 : 12] wb_am3 ; | |
661 | reg [31 : 12] wb_ta3 ; | |
662 | `else | |
663 | wire [2 : 0] wb_img_ctrl3_bit2_0 = 3'b000 ; | |
664 | wire [31 : 12] wb_ba3_bit31_12 = 20'h0000_0 ; | |
665 | wire wb_ba3_bit0 = 1'b0 ; | |
666 | wire [31 : 12] wb_am3 = 20'h0000_0 ; | |
667 | wire [31 : 12] wb_ta3 = 20'h0000_0 ; | |
668 | `endif | |
669 | `ifdef WB_IMAGE4 | |
670 | reg [2 : 0] wb_img_ctrl4_bit2_0 ; | |
671 | reg [31 : 12] wb_ba4_bit31_12 ; | |
672 | reg wb_ba4_bit0 ; | |
673 | reg [31 : 12] wb_am4 ; | |
674 | reg [31 : 12] wb_ta4 ; | |
675 | `else | |
676 | wire [2 : 0] wb_img_ctrl4_bit2_0 = 3'b000 ; | |
677 | wire [31 : 12] wb_ba4_bit31_12 = 20'h0000_0 ; | |
678 | wire wb_ba4_bit0 = 1'b0 ; | |
679 | wire [31 : 12] wb_am4 = 20'h0000_0 ; | |
680 | wire [31 : 12] wb_ta4 = 20'h0000_0 ; | |
681 | `endif | |
682 | `ifdef WB_IMAGE5 | |
683 | reg [2 : 0] wb_img_ctrl5_bit2_0 ; | |
684 | reg [31 : 12] wb_ba5_bit31_12 ; | |
685 | reg wb_ba5_bit0 ; | |
686 | reg [31 : 12] wb_am5 ; | |
687 | reg [31 : 12] wb_ta5 ; | |
688 | `else | |
689 | wire [2 : 0] wb_img_ctrl5_bit2_0 = 3'b000 ; | |
690 | wire [31 : 12] wb_ba5_bit31_12 = 20'h0000_0 ; | |
691 | wire wb_ba5_bit0 = 1'b0 ; | |
692 | wire [31 : 12] wb_am5 = 20'h0000_0 ; | |
693 | wire [31 : 12] wb_ta5 = 20'h0000_0 ; | |
694 | `endif | |
695 | reg [31 : 24] wb_err_cs_bit31_24 ; | |
696 | /* reg wb_err_cs_bit10 ;*/ | |
697 | reg wb_err_cs_bit9 ; | |
698 | reg wb_err_cs_bit8 ; | |
699 | reg wb_err_cs_bit0 ; | |
700 | reg [31 : 0] wb_err_addr ; | |
701 | reg [31 : 0] wb_err_data ; | |
702 | ||
703 | ||
704 | /*########################################################################################################### | |
705 | ------------------------------------------------------------------------------------------------------------- | |
706 | Configuration Cycle address register | |
707 | There are also some registers with NOT all bits implemented and therefor uses _bitX or _bitX2_X1 to | |
708 | sign which bit or range of bits are implemented. | |
709 | ------------------------------------------------------------------------------------------------------------- | |
710 | ###########################################################################################################*/ | |
711 | ||
712 | /*----------------------------------------------------------------------------------------------------------- | |
713 | [860h-868h] | |
714 | PCI bridge must ignore Type 1 configuration cycles (Master Abort) since they are used for PCI to PCI | |
715 | bridges. This is single function device, that means responding on configuration cycles to all functions | |
716 | (or responding only to function 0). Configuration address register for generating configuration cycles | |
717 | is prepared for all options (it includes Bus Number, Device, Function, Offset and Type). | |
718 | Interrupt acknowledge register stores interrupt vector data returned during Interrupt Acknowledge cycle. | |
719 | -----------------------------------------------------------------------------------------------------------*/ | |
720 | `ifdef HOST | |
721 | reg [23 : 2] cnf_addr_bit23_2 ; | |
722 | reg cnf_addr_bit0 ; | |
723 | `else // GUEST | |
724 | wire [23 : 2] cnf_addr_bit23_2 = 22'h0 ; | |
725 | wire cnf_addr_bit0 = 1'b0 ; | |
726 | `endif | |
727 | // reg [31 : 0] cnf_data ; IMPLEMENTED elsewhere !!!!! | |
728 | // reg [31 : 0] int_ack ; IMPLEMENTED elsewhere !!!!! | |
729 | ||
730 | ||
731 | /*########################################################################################################### | |
732 | ------------------------------------------------------------------------------------------------------------- | |
733 | General Interrupt registers | |
734 | There are also some registers with NOT all bits implemented and therefor uses _bitX or _bitX2_X1 to | |
735 | sign which bit or range of bits are implemented. | |
736 | ------------------------------------------------------------------------------------------------------------- | |
737 | ###########################################################################################################*/ | |
738 | ||
739 | /*----------------------------------------------------------------------------------------------------------- | |
740 | [FF8h-FFCh] | |
741 | Bit 31 in the Interrupt Control register is set by software and used to generate SOFT RESET. Other 4 | |
742 | bits are used to enable interrupt generations. | |
743 | 5 LSbits in the Interrupt Status register are indicating System Error Int, Parity Error Int, PCI & WB | |
744 | Error Int and Inerrupt respecively. System and Parity errors are implented only in HOST bridge | |
745 | implementations! | |
746 | -----------------------------------------------------------------------------------------------------------*/ | |
747 | reg icr_bit31 ; | |
748 | `ifdef HOST | |
749 | reg [4 : 3] icr_bit4_3 ; | |
750 | reg [4 : 3] isr_bit4_3 ; | |
751 | reg [2 : 0] icr_bit2_0 ; | |
752 | reg [2 : 0] isr_bit2_0 ; | |
753 | `else // GUEST | |
754 | wire [4 : 3] icr_bit4_3 = 2'h0 ; | |
755 | wire [4 : 3] isr_bit4_3 = 2'h0 ; | |
756 | reg [2 : 0] icr_bit2_0 ; | |
757 | reg [2 : 0] isr_bit2_0 ; | |
758 | `endif | |
759 | ||
760 | /*########################################################################################################### | |
761 | ------------------------------------------------------------------------------------------------------------- | |
762 | Initialization complete identifier | |
763 | When using I2C or similar initialisation mechanism, | |
764 | the bridge must not respond to transaction requests on PCI bus, | |
765 | not even to configuration cycles. | |
766 | Therefore, only when init_complete is set, the bridge starts | |
767 | participating on the PCI bus as an active device. | |
768 | Two additional flip flops are also provided for GUEST implementation, | |
769 | to synchronize to the pci clock after PCI reset is asynchronously de-asserted. | |
770 | ------------------------------------------------------------------------------------------------------------- | |
771 | ###########################################################################################################*/ | |
772 | ||
773 | `ifdef GUEST | |
774 | ||
775 | reg rst_inactive_sync ; | |
776 | reg rst_inactive ; | |
777 | ||
778 | `else | |
779 | ||
780 | wire rst_inactive = 1'b1 ; | |
781 | ||
782 | `endif | |
783 | ||
784 | reg init_complete ; | |
785 | ||
786 | wire sync_init_complete ; | |
787 | ||
788 | `ifdef HOST | |
789 | assign wb_init_complete_out = init_complete ; | |
790 | ||
791 | pci_synchronizer_flop #(1, 0) i_pci_init_complete_sync | |
792 | ( | |
793 | .data_in ( init_complete ), | |
794 | .clk_out ( pci_clk ), | |
795 | .sync_data_out ( sync_init_complete ), | |
796 | .async_reset ( reset ) | |
797 | ); | |
798 | ||
799 | reg pci_init_complete_out ; | |
800 | ||
801 | always@(posedge pci_clk or posedge reset) | |
802 | begin | |
803 | if (reset) | |
804 | pci_init_complete_out <= 1'b0 ; | |
805 | else | |
806 | pci_init_complete_out <= sync_init_complete ; | |
807 | end | |
808 | ||
809 | `endif | |
810 | ||
811 | `ifdef GUEST | |
812 | ||
813 | assign pci_init_complete_out = init_complete ; | |
814 | ||
815 | pci_synchronizer_flop #(1, 0) i_wb_init_complete_sync | |
816 | ( | |
817 | .data_in ( init_complete ), | |
818 | .clk_out ( wb_clk ), | |
819 | .sync_data_out ( sync_init_complete ), | |
820 | .async_reset ( reset ) | |
821 | ); | |
822 | ||
823 | reg wb_init_complete_out ; | |
824 | ||
825 | always@(posedge wb_clk or posedge reset) | |
826 | begin | |
827 | if (reset) | |
828 | wb_init_complete_out <= 1'b0 ; | |
829 | else | |
830 | wb_init_complete_out <= sync_init_complete ; | |
831 | end | |
832 | ||
833 | `endif | |
834 | ||
835 | /*########################################################################################################### | |
836 | ------------------------------------------------------------------------------------------------------------- | |
837 | ||
838 | ||
839 | -----------------------------------------------------------------------------------------------------------*/ | |
840 | ||
841 | `ifdef NO_CNF_IMAGE // if IMAGE0 is assigned as general image space | |
842 | ||
843 | assign r_conf_data_out = 32'h0000_0000 ; | |
844 | ||
845 | `else | |
846 | ||
847 | always@(r_conf_address_in or | |
848 | status_bit15_11 or status_bit8 or r_status_bit4 or command_bit8 or command_bit6 or command_bit2_0 or | |
849 | latency_timer or cache_line_size_reg or r_vendor_id or r_device_id or r_revision_id or | |
850 | r_subsys_vendor_id or r_subsys_id or r_max_lat or r_min_gnt or | |
851 | pci_ba0_bit31_8 or | |
852 | pci_img_ctrl0_bit2_1 or pci_am0 or pci_ta0 or pci_ba0_bit0 or | |
853 | pci_img_ctrl1_bit2_1 or pci_am1 or pci_ta1 or pci_ba1_bit31_8 or pci_ba1_bit0 or | |
854 | pci_img_ctrl2_bit2_1 or pci_am2 or pci_ta2 or pci_ba2_bit31_8 or pci_ba2_bit0 or | |
855 | pci_img_ctrl3_bit2_1 or pci_am3 or pci_ta3 or pci_ba3_bit31_8 or pci_ba3_bit0 or | |
856 | pci_img_ctrl4_bit2_1 or pci_am4 or pci_ta4 or pci_ba4_bit31_8 or pci_ba4_bit0 or | |
857 | pci_img_ctrl5_bit2_1 or pci_am5 or pci_ta5 or pci_ba5_bit31_8 or pci_ba5_bit0 or | |
858 | interrupt_line or | |
859 | pci_err_cs_bit31_24 or pci_err_cs_bit10 or pci_err_cs_bit9 or pci_err_cs_bit8 or pci_err_cs_bit0 or | |
860 | pci_err_addr or pci_err_data or | |
861 | wb_ba0_bit31_12 or wb_ba0_bit0 or | |
862 | wb_img_ctrl1_bit2_0 or wb_ba1_bit31_12 or wb_ba1_bit0 or wb_am1 or wb_ta1 or | |
863 | wb_img_ctrl2_bit2_0 or wb_ba2_bit31_12 or wb_ba2_bit0 or wb_am2 or wb_ta2 or | |
864 | wb_img_ctrl3_bit2_0 or wb_ba3_bit31_12 or wb_ba3_bit0 or wb_am3 or wb_ta3 or | |
865 | wb_img_ctrl4_bit2_0 or wb_ba4_bit31_12 or wb_ba4_bit0 or wb_am4 or wb_ta4 or | |
866 | wb_img_ctrl5_bit2_0 or wb_ba5_bit31_12 or wb_ba5_bit0 or wb_am5 or wb_ta5 or | |
867 | wb_err_cs_bit31_24 or /*wb_err_cs_bit10 or*/ wb_err_cs_bit9 or wb_err_cs_bit8 or wb_err_cs_bit0 or | |
868 | wb_err_addr or wb_err_data or | |
869 | cnf_addr_bit23_2 or cnf_addr_bit0 or icr_bit31 or icr_bit4_3 or icr_bit2_0 or isr_bit4_3 or isr_bit2_0 | |
870 | ||
871 | `ifdef PCI_CPCI_HS_IMPLEMENT | |
872 | or hs_ins or hs_ext or hs_pi or hs_loo or hs_eim or hs_cap_id | |
873 | `endif | |
874 | ||
875 | `ifdef PCI_SPOCI | |
876 | or spoci_cs_nack or spoci_cs_write or spoci_cs_read or spoci_cs_adr or spoci_cs_dat | |
877 | `endif | |
878 | ) | |
879 | begin | |
880 | case (r_conf_address_in[9:2]) | |
881 | // PCI header - configuration space | |
882 | 8'h0: r_conf_data_out = { r_device_id, r_vendor_id } ; | |
883 | 8'h1: r_conf_data_out = { status_bit15_11, r_status_bit10_9, status_bit8, r_status_bit7, 1'h0, r_status_bit5, r_status_bit4, | |
884 | 4'h0, 7'h00, command_bit8, 1'h0, command_bit6, 3'h0, command_bit2_0 } ; | |
885 | 8'h2: r_conf_data_out = { r_class_code, r_revision_id } ; | |
886 | 8'h3: r_conf_data_out = { 8'h00, r_header_type, latency_timer, cache_line_size_reg } ; | |
887 | 8'h4: | |
888 | begin | |
889 | `ifdef HOST | |
890 | `ifdef NO_CNF_IMAGE | |
891 | r_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_ba0_bit31_8[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] & | |
892 | pci_am0[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ; | |
893 | r_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):1] = 0 ; | |
894 | r_conf_data_out[0] = pci_ba0_bit0 & pci_am0[31]; | |
895 | `else | |
896 | r_conf_data_out[31:12] = pci_ba0_bit31_8[31:12] ; | |
897 | r_conf_data_out[11: 0] = 12'h000 ; | |
898 | `endif | |
899 | `endif | |
900 | ||
901 | `ifdef GUEST | |
902 | r_conf_data_out[31:12] = pci_ba0_bit31_8[31:12] ; | |
903 | r_conf_data_out[11: 0] = 12'h000 ; | |
904 | `endif | |
905 | end | |
906 | 8'h5: | |
907 | begin | |
908 | r_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_ba1_bit31_8[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] & | |
909 | pci_am1[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ; | |
910 | r_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):1] = 0 ; | |
911 | r_conf_data_out[0] = pci_ba1_bit0 & pci_am1[31]; | |
912 | end | |
913 | 8'h6: | |
914 | begin | |
915 | r_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_ba2_bit31_8[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] & | |
916 | pci_am2[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ; | |
917 | r_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):1] = 0 ; | |
918 | r_conf_data_out[0] = pci_ba2_bit0 & pci_am2[31]; | |
919 | end | |
920 | 8'h7: | |
921 | begin | |
922 | r_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_ba3_bit31_8[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] & | |
923 | pci_am3[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ; | |
924 | r_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):1] = 0 ; | |
925 | r_conf_data_out[0] = pci_ba3_bit0 & pci_am3[31]; | |
926 | end | |
927 | 8'h8: | |
928 | begin | |
929 | r_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_ba4_bit31_8[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] & | |
930 | pci_am4[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ; | |
931 | r_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):1] = 0 ; | |
932 | r_conf_data_out[0] = pci_ba4_bit0 & pci_am4[31]; | |
933 | end | |
934 | 8'h9: | |
935 | begin | |
936 | r_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_ba5_bit31_8[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] & | |
937 | pci_am5[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ; | |
938 | r_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):1] = 0 ; | |
939 | r_conf_data_out[0] = pci_ba5_bit0 & pci_am5[31]; | |
940 | end | |
941 | 8'hB: | |
942 | begin | |
943 | r_conf_data_out = {r_subsys_id, r_subsys_vendor_id} ; | |
944 | end | |
945 | `ifdef PCI_CPCI_HS_IMPLEMENT | |
946 | 8'hD: | |
947 | begin | |
948 | r_conf_data_out = {24'h0000_00, `PCI_CAP_PTR_VAL} ; | |
949 | end | |
950 | `endif | |
951 | 8'hf: r_conf_data_out = { r_max_lat, r_min_gnt, r_interrupt_pin, interrupt_line } ; | |
952 | `ifdef PCI_CPCI_HS_IMPLEMENT | |
953 | (`PCI_CAP_PTR_VAL >> 2): | |
954 | begin | |
955 | r_conf_data_out = {8'h00, hs_ins, hs_ext, hs_pi, hs_loo, 1'b0, hs_eim, 1'b0, 8'h00, hs_cap_id} ; | |
956 | end | |
957 | `endif | |
958 | // PCI target - configuration space | |
959 | {2'b01, `P_IMG_CTRL0_ADDR}: r_conf_data_out = { 29'h00000000, pci_img_ctrl0_bit2_1, 1'h0 } ; | |
960 | {2'b01, `P_BA0_ADDR} : | |
961 | begin | |
962 | `ifdef HOST | |
963 | `ifdef NO_CNF_IMAGE | |
964 | r_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_ba0_bit31_8[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] & | |
965 | pci_am0[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ; | |
966 | r_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):1] = 0 ; | |
967 | r_conf_data_out[0] = pci_ba0_bit0 & pci_am0[31]; | |
968 | `else | |
969 | r_conf_data_out[31:12] = pci_ba0_bit31_8[31:12] ; | |
970 | r_conf_data_out[11: 0] = 12'h000 ; | |
971 | `endif | |
972 | `endif | |
973 | ||
974 | `ifdef GUEST | |
975 | r_conf_data_out[31:12] = pci_ba0_bit31_8[31:12] ; | |
976 | r_conf_data_out[11: 0] = 12'h000 ; | |
977 | `endif | |
978 | end | |
979 | {2'b01, `P_AM0_ADDR}: | |
980 | begin | |
981 | `ifdef HOST | |
982 | `ifdef NO_CNF_IMAGE | |
983 | r_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_am0[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ; | |
984 | r_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):0] = 0 ; | |
985 | `else | |
986 | r_conf_data_out[31:12] = pci_am0[31:12] ; | |
987 | r_conf_data_out[11: 0] = 12'h000 ; | |
988 | `endif | |
989 | `endif | |
990 | ||
991 | `ifdef GUEST | |
992 | r_conf_data_out[31:12] = pci_am0[31:12] ; | |
993 | r_conf_data_out[11: 0] = 12'h000 ; | |
994 | `endif | |
995 | end | |
996 | {2'b01, `P_TA0_ADDR}: | |
997 | begin | |
998 | r_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_ta0[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ; | |
999 | r_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):0] = 0 ; | |
1000 | end | |
1001 | {2'b01, `P_IMG_CTRL1_ADDR}: r_conf_data_out = { 29'h00000000, pci_img_ctrl1_bit2_1, 1'h0 } ; | |
1002 | {2'b01, `P_BA1_ADDR}: | |
1003 | begin | |
1004 | r_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_ba1_bit31_8[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] & | |
1005 | pci_am1[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ; | |
1006 | r_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):1] = 0 ; | |
1007 | r_conf_data_out[0] = pci_ba1_bit0 & pci_am1[31]; | |
1008 | end | |
1009 | {2'b01, `P_AM1_ADDR}: | |
1010 | begin | |
1011 | r_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_am1[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ; | |
1012 | r_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):0] = 0 ; | |
1013 | end | |
1014 | {2'b01, `P_TA1_ADDR}: | |
1015 | begin | |
1016 | r_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_ta1[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ; | |
1017 | r_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):0] = 0 ; | |
1018 | end | |
1019 | {2'b01, `P_IMG_CTRL2_ADDR}: r_conf_data_out = { 29'h00000000, pci_img_ctrl2_bit2_1, 1'h0 } ; | |
1020 | {2'b01, `P_BA2_ADDR}: | |
1021 | begin | |
1022 | r_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_ba2_bit31_8[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] & | |
1023 | pci_am2[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ; | |
1024 | r_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):1] = 0 ; | |
1025 | r_conf_data_out[0] = pci_ba2_bit0 & pci_am2[31]; | |
1026 | end | |
1027 | {2'b01, `P_AM2_ADDR}: | |
1028 | begin | |
1029 | r_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_am2[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ; | |
1030 | r_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):0] = 0 ; | |
1031 | end | |
1032 | {2'b01, `P_TA2_ADDR}: | |
1033 | begin | |
1034 | r_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_ta2[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ; | |
1035 | r_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):0] = 0 ; | |
1036 | end | |
1037 | {2'b01, `P_IMG_CTRL3_ADDR}: r_conf_data_out = { 29'h00000000, pci_img_ctrl3_bit2_1, 1'h0 } ; | |
1038 | {2'b01, `P_BA3_ADDR}: | |
1039 | begin | |
1040 | r_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_ba3_bit31_8[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] & | |
1041 | pci_am3[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ; | |
1042 | r_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):1] = 0 ; | |
1043 | r_conf_data_out[0] = pci_ba3_bit0 & pci_am3[31]; | |
1044 | end | |
1045 | {2'b01, `P_AM3_ADDR}: | |
1046 | begin | |
1047 | r_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_am3[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ; | |
1048 | r_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):0] = 0 ; | |
1049 | end | |
1050 | {2'b01, `P_TA3_ADDR}: | |
1051 | begin | |
1052 | r_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_ta3[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ; | |
1053 | r_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):0] = 0 ; | |
1054 | end | |
1055 | {2'b01, `P_IMG_CTRL4_ADDR}: r_conf_data_out = { 29'h00000000, pci_img_ctrl4_bit2_1, 1'h0 } ; | |
1056 | {2'b01, `P_BA4_ADDR}: | |
1057 | begin | |
1058 | r_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_ba4_bit31_8[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] & | |
1059 | pci_am4[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ; | |
1060 | r_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):1] = 0 ; | |
1061 | r_conf_data_out[0] = pci_ba4_bit0 & pci_am4[31]; | |
1062 | end | |
1063 | {2'b01, `P_AM4_ADDR}: | |
1064 | begin | |
1065 | r_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_am4[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ; | |
1066 | r_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):0] = 0 ; | |
1067 | end | |
1068 | {2'b01, `P_TA4_ADDR}: | |
1069 | begin | |
1070 | r_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_ta4[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ; | |
1071 | r_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):0] = 0 ; | |
1072 | end | |
1073 | {2'b01, `P_IMG_CTRL5_ADDR}: r_conf_data_out = { 29'h00000000, pci_img_ctrl5_bit2_1, 1'h0 } ; | |
1074 | {2'b01, `P_BA5_ADDR}: | |
1075 | begin | |
1076 | r_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_ba5_bit31_8[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] & | |
1077 | pci_am5[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ; | |
1078 | r_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):1] = 0 ; | |
1079 | r_conf_data_out[0] = pci_ba5_bit0 & pci_am5[31]; | |
1080 | end | |
1081 | {2'b01, `P_AM5_ADDR}: | |
1082 | begin | |
1083 | r_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_am5[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ; | |
1084 | r_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):0] = 0 ; | |
1085 | end | |
1086 | {2'b01, `P_TA5_ADDR}: | |
1087 | begin | |
1088 | r_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_ta5[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ; | |
1089 | r_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):0] = 0 ; | |
1090 | end | |
1091 | {2'b01, `P_ERR_CS_ADDR}: r_conf_data_out = { pci_err_cs_bit31_24, 13'h0000, pci_err_cs_bit10, pci_err_cs_bit9, | |
1092 | pci_err_cs_bit8, 7'h00, pci_err_cs_bit0 } ; | |
1093 | {2'b01, `P_ERR_ADDR_ADDR}: r_conf_data_out = pci_err_addr ; | |
1094 | {2'b01, `P_ERR_DATA_ADDR}: r_conf_data_out = pci_err_data ; | |
1095 | // WB slave - configuration space | |
1096 | {2'b01, `WB_CONF_SPC_BAR_ADDR}: r_conf_data_out = { wb_ba0_bit31_12, 11'h000, wb_ba0_bit0 } ; | |
1097 | {2'b01, `W_IMG_CTRL1_ADDR}: r_conf_data_out = { 29'h00000000, wb_img_ctrl1_bit2_0 } ; | |
1098 | {2'b01, `W_BA1_ADDR}: | |
1099 | begin | |
1100 | r_conf_data_out[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] = wb_ba1_bit31_12[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] & | |
1101 | wb_am1[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] ; | |
1102 | r_conf_data_out[(31-`WB_NUM_OF_DEC_ADDR_LINES):1] = 0 ; | |
1103 | r_conf_data_out[0] = wb_ba1_bit0 ; | |
1104 | end | |
1105 | {2'b01, `W_AM1_ADDR}: | |
1106 | begin | |
1107 | r_conf_data_out[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] = wb_am1[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] ; | |
1108 | r_conf_data_out[(31-`WB_NUM_OF_DEC_ADDR_LINES):0] = 0 ; | |
1109 | end | |
1110 | {2'b01, `W_TA1_ADDR}: | |
1111 | begin | |
1112 | r_conf_data_out[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] = wb_ta1[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] ; | |
1113 | r_conf_data_out[(31-`WB_NUM_OF_DEC_ADDR_LINES):0] = 0 ; | |
1114 | end | |
1115 | {2'b01, `W_IMG_CTRL2_ADDR}: r_conf_data_out = { 29'h00000000, wb_img_ctrl2_bit2_0 } ; | |
1116 | `W_BA2_ADDR : | |
1117 | begin | |
1118 | r_conf_data_out[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] = wb_ba2_bit31_12[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] & | |
1119 | wb_am2[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] ; | |
1120 | r_conf_data_out[(31-`WB_NUM_OF_DEC_ADDR_LINES):1] = 0 ; | |
1121 | r_conf_data_out[0] = wb_ba2_bit0 ; | |
1122 | end | |
1123 | {2'b01, `W_AM2_ADDR}: | |
1124 | begin | |
1125 | r_conf_data_out[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] = wb_am2[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] ; | |
1126 | r_conf_data_out[(31-`WB_NUM_OF_DEC_ADDR_LINES):0] = 0 ; | |
1127 | end | |
1128 | {2'b01, `W_TA2_ADDR}: | |
1129 | begin | |
1130 | r_conf_data_out[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] = wb_ta2[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] ; | |
1131 | r_conf_data_out[(31-`WB_NUM_OF_DEC_ADDR_LINES):0] = 0 ; | |
1132 | end | |
1133 | {2'b01, `W_IMG_CTRL3_ADDR}: r_conf_data_out = { 29'h00000000, wb_img_ctrl3_bit2_0 } ; | |
1134 | {2'b01, `W_BA3_ADDR}: | |
1135 | begin | |
1136 | r_conf_data_out[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] = wb_ba3_bit31_12[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] & | |
1137 | wb_am3[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] ; | |
1138 | r_conf_data_out[(31-`WB_NUM_OF_DEC_ADDR_LINES):1] = 0 ; | |
1139 | r_conf_data_out[0] = wb_ba3_bit0 ; | |
1140 | end | |
1141 | {2'b01, `W_AM3_ADDR}: | |
1142 | begin | |
1143 | r_conf_data_out[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] = wb_am3[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] ; | |
1144 | r_conf_data_out[(31-`WB_NUM_OF_DEC_ADDR_LINES):0] = 0 ; | |
1145 | end | |
1146 | {2'b01, `W_TA3_ADDR}: | |
1147 | begin | |
1148 | r_conf_data_out[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] = wb_ta3[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] ; | |
1149 | r_conf_data_out[(31-`WB_NUM_OF_DEC_ADDR_LINES):0] = 0 ; | |
1150 | end | |
1151 | {2'b01, `W_IMG_CTRL4_ADDR}: r_conf_data_out = { 29'h00000000, wb_img_ctrl4_bit2_0 } ; | |
1152 | {2'b01, `W_BA4_ADDR}: | |
1153 | begin | |
1154 | r_conf_data_out[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] = wb_ba4_bit31_12[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] & | |
1155 | wb_am4[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] ; | |
1156 | r_conf_data_out[(31-`WB_NUM_OF_DEC_ADDR_LINES):1] = 0 ; | |
1157 | r_conf_data_out[0] = wb_ba4_bit0 ; | |
1158 | end | |
1159 | {2'b01, `W_AM4_ADDR}: | |
1160 | begin | |
1161 | r_conf_data_out[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] = wb_am4[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] ; | |
1162 | r_conf_data_out[(31-`WB_NUM_OF_DEC_ADDR_LINES):0] = 0 ; | |
1163 | end | |
1164 | {2'b01, `W_TA4_ADDR}: | |
1165 | begin | |
1166 | r_conf_data_out[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] = wb_ta4[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] ; | |
1167 | r_conf_data_out[(31-`WB_NUM_OF_DEC_ADDR_LINES):0] = 0 ; | |
1168 | end | |
1169 | {2'b01, `W_IMG_CTRL5_ADDR}: r_conf_data_out = { 29'h00000000, wb_img_ctrl5_bit2_0 } ; | |
1170 | {2'b01, `W_BA5_ADDR}: | |
1171 | begin | |
1172 | r_conf_data_out[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] = wb_ba5_bit31_12[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] & | |
1173 | wb_am5[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] ; | |
1174 | r_conf_data_out[(31-`WB_NUM_OF_DEC_ADDR_LINES):1] = 0 ; | |
1175 | r_conf_data_out[0] = wb_ba5_bit0 ; | |
1176 | end | |
1177 | {2'b01, `W_AM5_ADDR}: | |
1178 | begin | |
1179 | r_conf_data_out[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] = wb_am5[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] ; | |
1180 | r_conf_data_out[(31-`WB_NUM_OF_DEC_ADDR_LINES):0] = 0 ; | |
1181 | end | |
1182 | {2'b01, `W_TA5_ADDR}: | |
1183 | begin | |
1184 | r_conf_data_out[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] = wb_ta5[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] ; | |
1185 | r_conf_data_out[(31-`WB_NUM_OF_DEC_ADDR_LINES):0] = 0 ; | |
1186 | end | |
1187 | {2'b01, `W_ERR_CS_ADDR}: r_conf_data_out = { wb_err_cs_bit31_24, /*13*/14'h0000, /*wb_err_cs_bit10,*/ | |
1188 | wb_err_cs_bit9, wb_err_cs_bit8, 7'h00, wb_err_cs_bit0 } ; | |
1189 | {2'b01, `W_ERR_ADDR_ADDR}: r_conf_data_out = wb_err_addr ; | |
1190 | {2'b01, `W_ERR_DATA_ADDR}: r_conf_data_out = wb_err_data ; | |
1191 | ||
1192 | {2'b01, `CNF_ADDR_ADDR}: r_conf_data_out = { 8'h00, cnf_addr_bit23_2, 1'h0, cnf_addr_bit0 } ; | |
1193 | // `CNF_DATA_ADDR: implemented elsewhere !!! | |
1194 | // `INT_ACK_ADDR : implemented elsewhere !!! | |
1195 | {2'b01, `ICR_ADDR}: r_conf_data_out = { icr_bit31, 26'h0000_000, icr_bit4_3, icr_bit2_0 } ; | |
1196 | {2'b01, `ISR_ADDR}: r_conf_data_out = { 27'h0000_000, isr_bit4_3, isr_bit2_0 } ; | |
1197 | ||
1198 | `ifdef PCI_SPOCI | |
1199 | 8'hff: r_conf_data_out = {spoci_cs_nack, 5'h0, spoci_cs_write, spoci_cs_read, | |
1200 | 5'h0, spoci_cs_adr[10:8], | |
1201 | spoci_cs_adr[7:0], | |
1202 | spoci_cs_dat[7:0]} ; | |
1203 | `endif | |
1204 | default : r_conf_data_out = 32'h0000_0000 ; | |
1205 | endcase | |
1206 | end | |
1207 | ||
1208 | `endif | |
1209 | ||
1210 | `ifdef PCI_SPOCI | |
1211 | reg [ 7: 0] spoci_reg_num ; | |
1212 | wire [11: 0] w_conf_address = init_complete ? w_conf_address_in : {2'b00, spoci_reg_num, 2'b00} ; | |
1213 | `else | |
1214 | wire [11: 0] w_conf_address = w_conf_address_in ; | |
1215 | wire [ 7: 0] spoci_reg_num = 'hff ; | |
1216 | `endif | |
1217 | ||
1218 | always@(w_conf_address or | |
1219 | status_bit15_11 or status_bit8 or r_status_bit4 or command_bit8 or command_bit6 or command_bit2_0 or | |
1220 | latency_timer or cache_line_size_reg or r_vendor_id or r_device_id or r_revision_id or | |
1221 | r_subsys_id or r_subsys_vendor_id or r_max_lat or r_min_gnt or | |
1222 | pci_ba0_bit31_8 or | |
1223 | pci_img_ctrl0_bit2_1 or pci_am0 or pci_ta0 or pci_ba0_bit0 or | |
1224 | pci_img_ctrl1_bit2_1 or pci_am1 or pci_ta1 or pci_ba1_bit31_8 or pci_ba1_bit0 or | |
1225 | pci_img_ctrl2_bit2_1 or pci_am2 or pci_ta2 or pci_ba2_bit31_8 or pci_ba2_bit0 or | |
1226 | pci_img_ctrl3_bit2_1 or pci_am3 or pci_ta3 or pci_ba3_bit31_8 or pci_ba3_bit0 or | |
1227 | pci_img_ctrl4_bit2_1 or pci_am4 or pci_ta4 or pci_ba4_bit31_8 or pci_ba4_bit0 or | |
1228 | pci_img_ctrl5_bit2_1 or pci_am5 or pci_ta5 or pci_ba5_bit31_8 or pci_ba5_bit0 or | |
1229 | interrupt_line or | |
1230 | pci_err_cs_bit31_24 or pci_err_cs_bit10 or pci_err_cs_bit9 or pci_err_cs_bit8 or pci_err_cs_bit0 or | |
1231 | pci_err_addr or pci_err_data or | |
1232 | wb_ba0_bit31_12 or wb_ba0_bit0 or | |
1233 | wb_img_ctrl1_bit2_0 or wb_ba1_bit31_12 or wb_ba1_bit0 or wb_am1 or wb_ta1 or | |
1234 | wb_img_ctrl2_bit2_0 or wb_ba2_bit31_12 or wb_ba2_bit0 or wb_am2 or wb_ta2 or | |
1235 | wb_img_ctrl3_bit2_0 or wb_ba3_bit31_12 or wb_ba3_bit0 or wb_am3 or wb_ta3 or | |
1236 | wb_img_ctrl4_bit2_0 or wb_ba4_bit31_12 or wb_ba4_bit0 or wb_am4 or wb_ta4 or | |
1237 | wb_img_ctrl5_bit2_0 or wb_ba5_bit31_12 or wb_ba5_bit0 or wb_am5 or wb_ta5 or | |
1238 | wb_err_cs_bit31_24 or /*wb_err_cs_bit10 or*/ wb_err_cs_bit9 or wb_err_cs_bit8 or wb_err_cs_bit0 or | |
1239 | wb_err_addr or wb_err_data or | |
1240 | cnf_addr_bit23_2 or cnf_addr_bit0 or icr_bit31 or icr_bit4_3 or icr_bit2_0 or isr_bit4_3 or isr_bit2_0 | |
1241 | ||
1242 | `ifdef PCI_CPCI_HS_IMPLEMENT | |
1243 | or hs_ins or hs_ext or hs_pi or hs_loo or hs_eim or hs_cap_id | |
1244 | `endif | |
1245 | ||
1246 | `ifdef PCI_SPOCI | |
1247 | or spoci_cs_nack or spoci_cs_write or spoci_cs_read or spoci_cs_adr or spoci_cs_dat | |
1248 | `endif | |
1249 | ) | |
1250 | begin | |
1251 | case (w_conf_address[9:2]) | |
1252 | 8'h0: | |
1253 | begin | |
1254 | w_conf_data_out = { r_device_id, r_vendor_id } ; | |
1255 | w_reg_select_dec = 57'h000_0000_0000_0000 ; // Read-Only register | |
1256 | end | |
1257 | 8'h1: // w_reg_select_dec bit 0 | |
1258 | begin | |
1259 | w_conf_data_out = { status_bit15_11, r_status_bit10_9, status_bit8, r_status_bit7, 1'h0, r_status_bit5, r_status_bit4, | |
1260 | 4'h0, 7'h00, command_bit8, 1'h0, command_bit6, 3'h0, command_bit2_0 } ; | |
1261 | w_reg_select_dec = 57'h000_0000_0000_0001 ; | |
1262 | end | |
1263 | 8'h2: | |
1264 | begin | |
1265 | w_conf_data_out = { r_class_code, r_revision_id } ; | |
1266 | w_reg_select_dec = 57'h000_0000_0000_0000 ; // Read-Only register | |
1267 | end | |
1268 | 8'h3: // w_reg_select_dec bit 1 | |
1269 | begin | |
1270 | w_conf_data_out = { 8'h00, r_header_type, latency_timer, cache_line_size_reg } ; | |
1271 | w_reg_select_dec = 57'h000_0000_0000_0002 ; | |
1272 | end | |
1273 | 8'h4: // w_reg_select_dec bit 4 | |
1274 | begin | |
1275 | `ifdef HOST | |
1276 | `ifdef NO_CNF_IMAGE | |
1277 | w_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_ba0_bit31_8[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] & | |
1278 | pci_am0[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ; | |
1279 | w_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):1] = 0 ; | |
1280 | w_conf_data_out[0] = pci_ba0_bit0 & pci_am0[31]; | |
1281 | `else | |
1282 | w_conf_data_out[31:12] = pci_ba0_bit31_8[31:12] ; | |
1283 | w_conf_data_out[11: 0] = 12'h000 ; | |
1284 | `endif | |
1285 | `endif | |
1286 | ||
1287 | `ifdef GUEST | |
1288 | w_conf_data_out[31:12] = pci_ba0_bit31_8[31:12] ; | |
1289 | w_conf_data_out[11: 0] = 12'h000 ; | |
1290 | `endif | |
1291 | w_reg_select_dec = 57'h000_0000_0000_0010 ; // The same for another address | |
1292 | end | |
1293 | 8'h5: // w_reg_select_dec bit 8 | |
1294 | begin | |
1295 | w_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_ba1_bit31_8[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] & | |
1296 | pci_am1[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ; | |
1297 | w_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):1] = 0 ; | |
1298 | w_conf_data_out[0] = pci_ba1_bit0 & pci_am1[31]; | |
1299 | w_reg_select_dec = 57'h000_0000_0000_0100 ; // The same for another address | |
1300 | end | |
1301 | 8'h6: // w_reg_select_dec bit 12 | |
1302 | begin | |
1303 | w_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_ba2_bit31_8[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] & | |
1304 | pci_am2[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ; | |
1305 | w_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):1] = 0 ; | |
1306 | w_conf_data_out[0] = pci_ba2_bit0 & pci_am2[31]; | |
1307 | w_reg_select_dec = 57'h000_0000_0000_1000 ; // The same for another address | |
1308 | end | |
1309 | 8'h7: // w_reg_select_dec bit 16 | |
1310 | begin | |
1311 | w_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_ba3_bit31_8[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] & | |
1312 | pci_am3[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ; | |
1313 | w_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):1] = 0 ; | |
1314 | w_conf_data_out[0] = pci_ba3_bit0 & pci_am3[31]; | |
1315 | w_reg_select_dec = 57'h000_0000_0001_0000 ; // The same for another address | |
1316 | end | |
1317 | 8'h8: // w_reg_select_dec bit 20 | |
1318 | begin | |
1319 | w_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_ba4_bit31_8[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] & | |
1320 | pci_am4[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ; | |
1321 | w_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):1] = 0 ; | |
1322 | w_conf_data_out[0] = pci_ba4_bit0 & pci_am4[31]; | |
1323 | w_reg_select_dec = 57'h000_0000_0010_0000 ; // The same for another address | |
1324 | end | |
1325 | 8'h9: // w_reg_select_dec bit 24 | |
1326 | begin | |
1327 | w_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_ba5_bit31_8[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] & | |
1328 | pci_am5[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ; | |
1329 | w_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):1] = 0 ; | |
1330 | w_conf_data_out[0] = pci_ba5_bit0 & pci_am5[31]; | |
1331 | w_reg_select_dec = 57'h000_0000_0100_0000 ; // The same for another address | |
1332 | end | |
1333 | 8'hB: | |
1334 | begin | |
1335 | w_conf_data_out = {r_subsys_id, r_subsys_vendor_id} ; | |
1336 | w_reg_select_dec = 57'h000_0000_0000_0000 ; | |
1337 | end | |
1338 | ||
1339 | `ifdef PCI_CPCI_HS_IMPLEMENT | |
1340 | 8'hD: | |
1341 | begin | |
1342 | w_conf_data_out = {24'h0000_00, `PCI_CAP_PTR_VAL} ; | |
1343 | w_reg_select_dec = 57'h000_0000_0000_0000 ; // Read-Only register | |
1344 | end | |
1345 | `endif | |
1346 | 8'hf: // w_reg_select_dec bit 2 | |
1347 | begin | |
1348 | w_conf_data_out = { r_max_lat, r_min_gnt, r_interrupt_pin, interrupt_line } ; | |
1349 | w_reg_select_dec = 57'h000_0000_0000_0004 ; | |
1350 | end | |
1351 | `ifdef PCI_CPCI_HS_IMPLEMENT | |
1352 | (`PCI_CAP_PTR_VAL >> 2): | |
1353 | begin | |
1354 | w_reg_select_dec = 57'h100_0000_0000_0000 ; | |
1355 | w_conf_data_out = {8'h00, hs_ins, hs_ext, hs_pi, hs_loo, 1'b0, hs_eim, 1'b0, 8'h00, hs_cap_id} ; | |
1356 | end | |
1357 | `endif | |
1358 | {2'b01, `P_IMG_CTRL0_ADDR}: // w_reg_select_dec bit 3 | |
1359 | begin | |
1360 | w_conf_data_out = { 29'h00000000, pci_img_ctrl0_bit2_1, 1'h0 } ; | |
1361 | w_reg_select_dec = 57'h000_0000_0000_0008 ; | |
1362 | end | |
1363 | {2'b01, `P_BA0_ADDR}: // w_reg_select_dec bit 4 | |
1364 | begin | |
1365 | `ifdef HOST | |
1366 | `ifdef NO_CNF_IMAGE | |
1367 | w_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_ba0_bit31_8[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] & | |
1368 | pci_am0[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ; | |
1369 | w_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):1] = 0 ; | |
1370 | w_conf_data_out[0] = pci_ba0_bit0 & pci_am0[31]; | |
1371 | `else | |
1372 | w_conf_data_out[31:12] = pci_ba0_bit31_8[31:12] ; | |
1373 | w_conf_data_out[11: 0] = 12'h000 ; | |
1374 | `endif | |
1375 | `endif | |
1376 | ||
1377 | `ifdef GUEST | |
1378 | w_conf_data_out[31:12] = pci_ba0_bit31_8[31:12] ; | |
1379 | w_conf_data_out[11: 0] = 12'h000 ; | |
1380 | `endif | |
1381 | w_reg_select_dec = 57'h000_0000_0000_0010 ; // The same for another address | |
1382 | end | |
1383 | {2'b01, `P_AM0_ADDR}: // w_reg_select_dec bit 5 | |
1384 | begin | |
1385 | `ifdef HOST | |
1386 | `ifdef NO_CNF_IMAGE | |
1387 | w_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_am0[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ; | |
1388 | w_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):0] = 0 ; | |
1389 | `else | |
1390 | w_conf_data_out[31:12] = pci_am0[31:12] ; | |
1391 | w_conf_data_out[11: 0] = 12'h000 ; | |
1392 | `endif | |
1393 | `endif | |
1394 | ||
1395 | `ifdef GUEST | |
1396 | w_conf_data_out[31:12] = pci_am0[31:12] ; | |
1397 | w_conf_data_out[11: 0] = 12'h000 ; | |
1398 | `endif | |
1399 | w_reg_select_dec = 57'h000_0000_0000_0020 ; | |
1400 | end | |
1401 | {2'b01, `P_TA0_ADDR}: // w_reg_select_dec bit 6 | |
1402 | begin | |
1403 | w_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_ta0[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ; | |
1404 | w_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):0] = 0 ; | |
1405 | w_reg_select_dec = 57'h000_0000_0000_0040 ; | |
1406 | end | |
1407 | {2'b01, `P_IMG_CTRL1_ADDR}: // w_reg_select_dec bit 7 | |
1408 | begin | |
1409 | w_conf_data_out = { 29'h00000000, pci_img_ctrl1_bit2_1, 1'h0 } ; | |
1410 | w_reg_select_dec = 57'h000_0000_0000_0080 ; | |
1411 | end | |
1412 | {2'b01, `P_BA1_ADDR}: // w_reg_select_dec bit 8 | |
1413 | begin | |
1414 | w_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_ba1_bit31_8[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] & | |
1415 | pci_am1[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ; | |
1416 | w_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):1] = 0 ; | |
1417 | w_conf_data_out[0] = pci_ba1_bit0 & pci_am1[31]; | |
1418 | w_reg_select_dec = 57'h000_0000_0000_0100 ; // The same for another address | |
1419 | end | |
1420 | {2'b01, `P_AM1_ADDR}: // w_reg_select_dec bit 9 | |
1421 | begin | |
1422 | w_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_am1[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ; | |
1423 | w_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):0] = 0 ; | |
1424 | w_reg_select_dec = 57'h000_0000_0000_0200 ; | |
1425 | end | |
1426 | {2'b01, `P_TA1_ADDR}: // w_reg_select_dec bit 10 | |
1427 | begin | |
1428 | w_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_ta1[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ; | |
1429 | w_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):0] = 0 ; | |
1430 | w_reg_select_dec = 57'h000_0000_0000_0400 ; | |
1431 | end | |
1432 | {2'b01, `P_IMG_CTRL2_ADDR}: // w_reg_select_dec bit 11 | |
1433 | begin | |
1434 | w_conf_data_out = { 29'h00000000, pci_img_ctrl2_bit2_1, 1'h0 } ; | |
1435 | w_reg_select_dec = 57'h000_0000_0000_0800 ; | |
1436 | end | |
1437 | {2'b01, `P_BA2_ADDR}: // w_reg_select_dec bit 12 | |
1438 | begin | |
1439 | w_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_ba2_bit31_8[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] & | |
1440 | pci_am2[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ; | |
1441 | w_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):1] = 0 ; | |
1442 | w_conf_data_out[0] = pci_ba2_bit0 & pci_am2[31]; | |
1443 | w_reg_select_dec = 57'h000_0000_0000_1000 ; // The same for another address | |
1444 | end | |
1445 | {2'b01, `P_AM2_ADDR}: // w_reg_select_dec bit 13 | |
1446 | begin | |
1447 | w_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_am2[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ; | |
1448 | w_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):0] = 0 ; | |
1449 | w_reg_select_dec = 57'h000_0000_0000_2000 ; | |
1450 | end | |
1451 | {2'b01, `P_TA2_ADDR}: // w_reg_select_dec bit 14 | |
1452 | begin | |
1453 | w_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_ta2[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ; | |
1454 | w_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):0] = 0 ; | |
1455 | w_reg_select_dec = 57'h000_0000_0000_4000 ; | |
1456 | end | |
1457 | {2'b01, `P_IMG_CTRL3_ADDR}: // w_reg_select_dec bit 15 | |
1458 | begin | |
1459 | w_conf_data_out = { 29'h00000000, pci_img_ctrl3_bit2_1, 1'h0 } ; | |
1460 | w_reg_select_dec = 57'h000_0000_0000_8000 ; | |
1461 | end | |
1462 | {2'b01, `P_BA3_ADDR}: // w_reg_select_dec bit 16 | |
1463 | begin | |
1464 | w_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_ba3_bit31_8[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] & | |
1465 | pci_am3[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ; | |
1466 | w_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):1] = 0 ; | |
1467 | w_conf_data_out[0] = pci_ba3_bit0 & pci_am3[31]; | |
1468 | w_reg_select_dec = 57'h000_0000_0001_0000 ; // The same for another address | |
1469 | end | |
1470 | {2'b01, `P_AM3_ADDR}: // w_reg_select_dec bit 17 | |
1471 | begin | |
1472 | w_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_am3[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ; | |
1473 | w_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):0] = 0 ; | |
1474 | w_reg_select_dec = 57'h000_0000_0002_0000 ; | |
1475 | end | |
1476 | {2'b01, `P_TA3_ADDR}: // w_reg_select_dec bit 18 | |
1477 | begin | |
1478 | w_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_ta3[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ; | |
1479 | w_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):0] = 0 ; | |
1480 | w_reg_select_dec = 57'h000_0000_0004_0000 ; | |
1481 | end | |
1482 | {2'b01, `P_IMG_CTRL4_ADDR}: // w_reg_select_dec bit 19 | |
1483 | begin | |
1484 | w_conf_data_out = { 29'h00000000, pci_img_ctrl4_bit2_1, 1'h0 } ; | |
1485 | w_reg_select_dec = 57'h000_0000_0008_0000 ; | |
1486 | end | |
1487 | {2'b01, `P_BA4_ADDR}: // w_reg_select_dec bit 20 | |
1488 | begin | |
1489 | w_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_ba4_bit31_8[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] & | |
1490 | pci_am4[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ; | |
1491 | w_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):1] = 0 ; | |
1492 | w_conf_data_out[0] = pci_ba4_bit0 & pci_am4[31]; | |
1493 | w_reg_select_dec = 57'h000_0000_0010_0000 ; // The same for another address | |
1494 | end | |
1495 | {2'b01, `P_AM4_ADDR}: // w_reg_select_dec bit 21 | |
1496 | begin | |
1497 | w_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_am4[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ; | |
1498 | w_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):0] = 0 ; | |
1499 | w_reg_select_dec = 57'h000_0000_0020_0000 ; | |
1500 | end | |
1501 | {2'b01, `P_TA4_ADDR}: // w_reg_select_dec bit 22 | |
1502 | begin | |
1503 | w_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_ta4[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ; | |
1504 | w_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):0] = 0 ; | |
1505 | w_reg_select_dec = 57'h000_0000_0040_0000 ; | |
1506 | end | |
1507 | {2'b01, `P_IMG_CTRL5_ADDR}: // w_reg_select_dec bit 23 | |
1508 | begin | |
1509 | w_conf_data_out = { 29'h00000000, pci_img_ctrl5_bit2_1, 1'h0 } ; | |
1510 | w_reg_select_dec = 57'h000_0000_0080_0000 ; | |
1511 | end | |
1512 | {2'b01, `P_BA5_ADDR}: // w_reg_select_dec bit 24 | |
1513 | begin | |
1514 | w_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_ba5_bit31_8[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] & | |
1515 | pci_am5[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ; | |
1516 | w_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):1] = 0 ; | |
1517 | w_conf_data_out[0] = pci_ba5_bit0 & pci_am5[31]; | |
1518 | w_reg_select_dec = 57'h000_0000_0100_0000 ; // The same for another address | |
1519 | end | |
1520 | {2'b01, `P_AM5_ADDR}: // w_reg_select_dec bit 25 | |
1521 | begin | |
1522 | w_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_am5[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ; | |
1523 | w_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):0] = 0 ; | |
1524 | w_reg_select_dec = 57'h000_0000_0200_0000 ; | |
1525 | end | |
1526 | {2'b01, `P_TA5_ADDR}: // w_reg_select_dec bit 26 | |
1527 | begin | |
1528 | w_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_ta5[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ; | |
1529 | w_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):0] = 0 ; | |
1530 | w_reg_select_dec = 57'h000_0000_0400_0000 ; | |
1531 | end | |
1532 | {2'b01, `P_ERR_CS_ADDR}: // w_reg_select_dec bit 27 | |
1533 | begin | |
1534 | w_conf_data_out = { pci_err_cs_bit31_24, 13'h0000, pci_err_cs_bit10, pci_err_cs_bit9, | |
1535 | pci_err_cs_bit8, 7'h00, pci_err_cs_bit0 } ; | |
1536 | w_reg_select_dec = 57'h000_0000_0800_0000 ; | |
1537 | end | |
1538 | {2'b01, `P_ERR_ADDR_ADDR}: // w_reg_select_dec bit 28 | |
1539 | begin | |
1540 | w_conf_data_out = pci_err_addr ; | |
1541 | w_reg_select_dec = 57'h000_0000_0000_0000 ; // = 56'h00_0000_1000_0000 ; | |
1542 | end | |
1543 | {2'b01, `P_ERR_DATA_ADDR}: // w_reg_select_dec bit 29 | |
1544 | begin | |
1545 | w_conf_data_out = pci_err_data ; | |
1546 | w_reg_select_dec = 57'h000_0000_0000_0000 ; // = 56'h00_0000_2000_0000 ; | |
1547 | end | |
1548 | // WB slave - configuration space | |
1549 | {2'b01, `WB_CONF_SPC_BAR_ADDR}: | |
1550 | begin | |
1551 | w_conf_data_out = { wb_ba0_bit31_12, 11'h000, wb_ba0_bit0 } ; | |
1552 | w_reg_select_dec = 57'h000_0000_0000_0000 ; // Read-Only register | |
1553 | end | |
1554 | {2'b01, `W_IMG_CTRL1_ADDR}: // w_reg_select_dec bit 30 | |
1555 | begin | |
1556 | w_conf_data_out = { 29'h00000000, wb_img_ctrl1_bit2_0 } ; | |
1557 | w_reg_select_dec = 57'h000_0000_4000_0000 ; | |
1558 | end | |
1559 | {2'b01, `W_BA1_ADDR}: // w_reg_select_dec bit 31 | |
1560 | begin | |
1561 | w_conf_data_out[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] = wb_ba1_bit31_12[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] & | |
1562 | wb_am1[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] ; | |
1563 | w_conf_data_out[(31-`WB_NUM_OF_DEC_ADDR_LINES):1] = 0 ; | |
1564 | w_conf_data_out[0] = wb_ba1_bit0 ; | |
1565 | w_reg_select_dec = 57'h000_0000_8000_0000 ; | |
1566 | end | |
1567 | {2'b01, `W_AM1_ADDR}: // w_reg_select_dec bit 32 | |
1568 | begin | |
1569 | w_conf_data_out[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] = wb_am1[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] ; | |
1570 | w_conf_data_out[(31-`WB_NUM_OF_DEC_ADDR_LINES):0] = 0 ; | |
1571 | w_reg_select_dec = 57'h000_0001_0000_0000 ; | |
1572 | end | |
1573 | {2'b01, `W_TA1_ADDR}: // w_reg_select_dec bit 33 | |
1574 | begin | |
1575 | w_conf_data_out[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] = wb_ta1[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] ; | |
1576 | w_conf_data_out[(31-`WB_NUM_OF_DEC_ADDR_LINES):0] = 0 ; | |
1577 | w_reg_select_dec = 57'h000_0002_0000_0000 ; | |
1578 | end | |
1579 | {2'b01, `W_IMG_CTRL2_ADDR}: // w_reg_select_dec bit 34 | |
1580 | begin | |
1581 | w_conf_data_out = { 29'h00000000, wb_img_ctrl2_bit2_0 } ; | |
1582 | w_reg_select_dec = 57'h000_0004_0000_0000 ; | |
1583 | end | |
1584 | {2'b01, `W_BA2_ADDR}: // w_reg_select_dec bit 35 | |
1585 | begin | |
1586 | w_conf_data_out[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] = wb_ba2_bit31_12[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] & | |
1587 | wb_am2[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] ; | |
1588 | w_conf_data_out[(31-`WB_NUM_OF_DEC_ADDR_LINES):1] = 0 ; | |
1589 | w_conf_data_out[0] = wb_ba2_bit0 ; | |
1590 | w_reg_select_dec = 57'h000_0008_0000_0000 ; | |
1591 | end | |
1592 | {2'b01, `W_AM2_ADDR}: // w_reg_select_dec bit 36 | |
1593 | begin | |
1594 | w_conf_data_out[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] = wb_am2[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] ; | |
1595 | w_conf_data_out[(31-`WB_NUM_OF_DEC_ADDR_LINES):0] = 0 ; | |
1596 | w_reg_select_dec = 57'h000_0010_0000_0000 ; | |
1597 | end | |
1598 | {2'b01, `W_TA2_ADDR}: // w_reg_select_dec bit 37 | |
1599 | begin | |
1600 | w_conf_data_out[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] = wb_ta2[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] ; | |
1601 | w_conf_data_out[(31-`WB_NUM_OF_DEC_ADDR_LINES):0] = 0 ; | |
1602 | w_reg_select_dec = 57'h000_0020_0000_0000 ; | |
1603 | end | |
1604 | {2'b01, `W_IMG_CTRL3_ADDR}: // w_reg_select_dec bit 38 | |
1605 | begin | |
1606 | w_conf_data_out = { 29'h00000000, wb_img_ctrl3_bit2_0 } ; | |
1607 | w_reg_select_dec = 57'h000_0040_0000_0000 ; | |
1608 | end | |
1609 | {2'b01, `W_BA3_ADDR}: // w_reg_select_dec bit 39 | |
1610 | begin | |
1611 | w_conf_data_out[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] = wb_ba3_bit31_12[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] & | |
1612 | wb_am3[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] ; | |
1613 | w_conf_data_out[(31-`WB_NUM_OF_DEC_ADDR_LINES):1] = 0 ; | |
1614 | w_conf_data_out[0] = wb_ba3_bit0 ; | |
1615 | w_reg_select_dec = 57'h000_0080_0000_0000 ; | |
1616 | end | |
1617 | {2'b01, `W_AM3_ADDR}: // w_reg_select_dec bit 40 | |
1618 | begin | |
1619 | w_conf_data_out[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] = wb_am3[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] ; | |
1620 | w_conf_data_out[(31-`WB_NUM_OF_DEC_ADDR_LINES):0] = 0 ; | |
1621 | w_reg_select_dec = 57'h000_0100_0000_0000 ; | |
1622 | end | |
1623 | {2'b01, `W_TA3_ADDR}: // w_reg_select_dec bit 41 | |
1624 | begin | |
1625 | w_conf_data_out[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] = wb_ta3[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] ; | |
1626 | w_conf_data_out[(31-`WB_NUM_OF_DEC_ADDR_LINES):0] = 0 ; | |
1627 | w_reg_select_dec = 57'h000_0200_0000_0000 ; | |
1628 | end | |
1629 | {2'b01, `W_IMG_CTRL4_ADDR}: // w_reg_select_dec bit 42 | |
1630 | begin | |
1631 | w_conf_data_out = { 29'h00000000, wb_img_ctrl4_bit2_0 } ; | |
1632 | w_reg_select_dec = 57'h000_0400_0000_0000 ; | |
1633 | end | |
1634 | {2'b01, `W_BA4_ADDR}: // w_reg_select_dec bit 43 | |
1635 | begin | |
1636 | w_conf_data_out[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] = wb_ba4_bit31_12[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] & | |
1637 | wb_am4[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] ; | |
1638 | w_conf_data_out[(31-`WB_NUM_OF_DEC_ADDR_LINES):1] = 0 ; | |
1639 | w_conf_data_out[0] = wb_ba4_bit0 ; | |
1640 | w_reg_select_dec = 57'h000_0800_0000_0000 ; | |
1641 | end | |
1642 | {2'b01, `W_AM4_ADDR}: // w_reg_select_dec bit 44 | |
1643 | begin | |
1644 | w_conf_data_out[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] = wb_am4[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] ; | |
1645 | w_conf_data_out[(31-`WB_NUM_OF_DEC_ADDR_LINES):0] = 0 ; | |
1646 | w_reg_select_dec = 57'h000_1000_0000_0000 ; | |
1647 | end | |
1648 | {2'b01, `W_TA4_ADDR}: // w_reg_select_dec bit 45 | |
1649 | begin | |
1650 | w_conf_data_out[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] = wb_ta4[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] ; | |
1651 | w_conf_data_out[(31-`WB_NUM_OF_DEC_ADDR_LINES):0] = 0 ; | |
1652 | w_reg_select_dec = 57'h000_2000_0000_0000 ; | |
1653 | end | |
1654 | {2'b01, `W_IMG_CTRL5_ADDR}: // w_reg_select_dec bit 46 | |
1655 | begin | |
1656 | w_conf_data_out = { 29'h00000000, wb_img_ctrl5_bit2_0 } ; | |
1657 | w_reg_select_dec = 57'h000_4000_0000_0000 ; | |
1658 | end | |
1659 | {2'b01, `W_BA5_ADDR}: // w_reg_select_dec bit 47 | |
1660 | begin | |
1661 | w_conf_data_out[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] = wb_ba5_bit31_12[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] & | |
1662 | wb_am5[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] ; | |
1663 | w_conf_data_out[(31-`WB_NUM_OF_DEC_ADDR_LINES):1] = 0 ; | |
1664 | w_conf_data_out[0] = wb_ba5_bit0 ; | |
1665 | w_reg_select_dec = 57'h000_8000_0000_0000 ; | |
1666 | end | |
1667 | {2'b01, `W_AM5_ADDR}: // w_reg_select_dec bit 48 | |
1668 | begin | |
1669 | w_conf_data_out[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] = wb_am5[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] ; | |
1670 | w_conf_data_out[(31-`WB_NUM_OF_DEC_ADDR_LINES):0] = 0 ; | |
1671 | w_reg_select_dec = 57'h001_0000_0000_0000 ; | |
1672 | end | |
1673 | {2'b01, `W_TA5_ADDR}: // w_reg_select_dec bit 49 | |
1674 | begin | |
1675 | w_conf_data_out[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] = wb_ta5[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] ; | |
1676 | w_conf_data_out[(31-`WB_NUM_OF_DEC_ADDR_LINES):0] = 0 ; | |
1677 | w_reg_select_dec = 57'h002_0000_0000_0000 ; | |
1678 | end | |
1679 | {2'b01, `W_ERR_CS_ADDR}: // w_reg_select_dec bit 50 | |
1680 | begin | |
1681 | w_conf_data_out = { wb_err_cs_bit31_24, /*13*/14'h0000, /*wb_err_cs_bit10,*/ | |
1682 | wb_err_cs_bit9, wb_err_cs_bit8, 7'h00, wb_err_cs_bit0 } ; | |
1683 | w_reg_select_dec = 57'h004_0000_0000_0000 ; | |
1684 | end | |
1685 | {2'b01, `W_ERR_ADDR_ADDR}: // w_reg_select_dec bit 51 | |
1686 | begin | |
1687 | w_conf_data_out = wb_err_addr ; | |
1688 | w_reg_select_dec = 57'h008_0000_0000_0000 ; | |
1689 | end | |
1690 | {2'b01, `W_ERR_DATA_ADDR}: // w_reg_select_dec bit 52 | |
1691 | begin | |
1692 | w_conf_data_out = wb_err_data ; | |
1693 | w_reg_select_dec = 57'h010_0000_0000_0000 ; | |
1694 | end | |
1695 | {2'b01, `CNF_ADDR_ADDR}: // w_reg_select_dec bit 53 | |
1696 | begin | |
1697 | w_conf_data_out = { 8'h00, cnf_addr_bit23_2, 1'h0, cnf_addr_bit0 } ; | |
1698 | w_reg_select_dec = 57'h020_0000_0000_0000 ; | |
1699 | end | |
1700 | // `CNF_DATA_ADDR: implemented elsewhere !!! | |
1701 | // `INT_ACK_ADDR: implemented elsewhere !!! | |
1702 | {2'b01, `ICR_ADDR}: // w_reg_select_dec bit 54 | |
1703 | begin | |
1704 | w_conf_data_out = { icr_bit31, 26'h0000_000, icr_bit4_3, icr_bit2_0 } ; | |
1705 | w_reg_select_dec = 57'h040_0000_0000_0000 ; | |
1706 | end | |
1707 | {2'b01, `ISR_ADDR}: // w_reg_select_dec bit 55 | |
1708 | begin | |
1709 | w_conf_data_out = { 27'h0000_000, isr_bit4_3, isr_bit2_0 } ; | |
1710 | w_reg_select_dec = 57'h080_0000_0000_0000 ; | |
1711 | end | |
1712 | ||
1713 | `ifdef PCI_SPOCI | |
1714 | 8'hff: | |
1715 | begin | |
1716 | w_conf_data_out = {spoci_cs_nack, 5'h0, spoci_cs_write, spoci_cs_read, | |
1717 | 5'h0, spoci_cs_adr[10:8], | |
1718 | spoci_cs_adr[7:0], | |
1719 | spoci_cs_dat[7:0]} ; | |
1720 | ||
1721 | // this register is implemented separate from other registers, because | |
1722 | // it has special features implemented | |
1723 | w_reg_select_dec = 57'h000_0000_0000_0000 ; | |
1724 | end | |
1725 | `endif | |
1726 | ||
1727 | default: | |
1728 | begin | |
1729 | w_conf_data_out = 32'h0000_0000 ; | |
1730 | w_reg_select_dec = 57'h000_0000_0000_0000 ; | |
1731 | end | |
1732 | endcase | |
1733 | end | |
1734 | ||
1735 | `ifdef PCI_SPOCI | |
1736 | reg init_we ; | |
1737 | reg init_cfg_done ; | |
1738 | reg [31: 0] spoci_dat ; | |
1739 | wire [31: 0] w_conf_data = init_cfg_done ? w_conf_data_in : spoci_dat ; | |
1740 | wire [ 3: 0] w_byte_en = init_cfg_done ? w_byte_en_in : 4'b0000 ; | |
1741 | `else | |
1742 | wire init_we = 1'b0 ; | |
1743 | wire init_cfg_done = 1'b1 ; | |
1744 | wire [31: 0] w_conf_data = w_conf_data_in ; | |
1745 | wire [ 3: 0] w_byte_en = w_byte_en_in ; | |
1746 | wire [31: 0] spoci_dat = 'h0000_0000 ; | |
1747 | `endif | |
1748 | ||
1749 | // Reduced write data for BASE, MASK and TRANSLATION registers of PCI and WB images | |
1750 | assign w_conf_pdata_reduced[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = w_conf_data[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ; | |
1751 | assign w_conf_pdata_reduced[(31-`PCI_NUM_OF_DEC_ADDR_LINES): 0] = 0 ; | |
1752 | assign w_conf_wdata_reduced[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] = w_conf_data[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] ; | |
1753 | assign w_conf_wdata_reduced[(31-`WB_NUM_OF_DEC_ADDR_LINES): 0] = 0 ; | |
1754 | ||
1755 | wire w_we = w_we_i | init_we ; | |
1756 | ||
1757 | always@(posedge w_clock or posedge reset) | |
1758 | begin | |
1759 | // Here are implemented all registers that are reset with RESET signal otherwise they can be normaly written!!! | |
1760 | // Registers that are commented are implemented after this alwasy statement, because they are e.g. reset with | |
1761 | // RESET signal, set with some status signal and they are erased with writting '1' into them !!! | |
1762 | if (reset) | |
1763 | begin | |
1764 | /*status_bit15_11 ; status_bit8 ;*/ command_bit8 <= 1'h0 ; command_bit6 <= 1'h0 ; command_bit2_0 <= 3'h0 ; | |
1765 | latency_timer <= 8'h00 ; cache_line_size_reg <= 8'h00 ; | |
1766 | // ALL pci_base address registers are the same as pci_baX registers ! | |
1767 | interrupt_line <= 8'h00 ; | |
1768 | ||
1769 | `ifdef HOST | |
1770 | `ifdef NO_CNF_IMAGE // if PCI bridge is HOST and IMAGE0 is assigned as general image space | |
1771 | `ifdef PCI_IMAGE0 | |
1772 | pci_img_ctrl0_bit2_1 <= {`PCI_AT_EN0, 1'b0} ; | |
1773 | pci_ba0_bit31_8 <= 24'h0000_00 ; | |
1774 | pci_ba0_bit0 <= `PCI_BA0_MEM_IO ; | |
1775 | pci_am0 <= `PCI_AM0 ; | |
1776 | pci_ta0 <= `PCI_TA0 ;//fr2201 translation address | |
1777 | `endif | |
1778 | `else | |
1779 | pci_ba0_bit31_8 <= 24'h0000_00 ; | |
1780 | `endif | |
1781 | `endif | |
1782 | ||
1783 | `ifdef GUEST | |
1784 | pci_ba0_bit31_8 <= 24'h0000_00 ; | |
1785 | `endif | |
1786 | ||
1787 | pci_img_ctrl1_bit2_1 <= {`PCI_AT_EN1, 1'b0} ; | |
1788 | ||
1789 | pci_ba1_bit31_8 <= 24'h0000_00 ; | |
1790 | `ifdef HOST | |
1791 | pci_ba1_bit0 <= `PCI_BA1_MEM_IO ; | |
1792 | `endif | |
1793 | pci_am1 <= `PCI_AM1; | |
1794 | pci_ta1 <= `PCI_TA1 ;//FR2201 translation address ; | |
1795 | `ifdef PCI_IMAGE2 | |
1796 | ||
1797 | pci_img_ctrl2_bit2_1 <= {`PCI_AT_EN2, 1'b0} ; | |
1798 | ||
1799 | pci_ba2_bit31_8 <= 24'h0000_00 ; | |
1800 | `ifdef HOST | |
1801 | pci_ba2_bit0 <= `PCI_BA2_MEM_IO ; | |
1802 | `endif | |
1803 | pci_am2 <= `PCI_AM2; | |
1804 | pci_ta2 <= `PCI_TA2 ;//FR2201 translation address ; | |
1805 | `endif | |
1806 | `ifdef PCI_IMAGE3 | |
1807 | ||
1808 | pci_img_ctrl3_bit2_1 <= {`PCI_AT_EN3, 1'b0} ; //FR2201 when defined enabled | |
1809 | ||
1810 | pci_ba3_bit31_8 <= 24'h0000_00 ; | |
1811 | `ifdef HOST | |
1812 | pci_ba3_bit0 <= `PCI_BA3_MEM_IO ; | |
1813 | `endif | |
1814 | pci_am3 <= `PCI_AM3; | |
1815 | pci_ta3 <= `PCI_TA3 ;//FR2201 translation address ; | |
1816 | `endif | |
1817 | `ifdef PCI_IMAGE4 | |
1818 | ||
1819 | pci_img_ctrl4_bit2_1 <= {`PCI_AT_EN4, 1'b0} ; //FR2201 when defined enabled | |
1820 | ||
1821 | pci_ba4_bit31_8 <= 24'h0000_00 ; | |
1822 | `ifdef HOST | |
1823 | pci_ba4_bit0 <= `PCI_BA4_MEM_IO ; | |
1824 | `endif | |
1825 | pci_am4 <= `PCI_AM4; | |
1826 | pci_ta4 <= `PCI_TA4 ;//FR2201 translation address ; | |
1827 | `endif | |
1828 | `ifdef PCI_IMAGE5 | |
1829 | ||
1830 | pci_img_ctrl5_bit2_1 <= {`PCI_AT_EN5, 1'b0} ; //FR2201 when defined enabled | |
1831 | ||
1832 | pci_ba5_bit31_8 <= 24'h0000_00 ; | |
1833 | `ifdef HOST | |
1834 | pci_ba5_bit0 <= `PCI_BA5_MEM_IO ; | |
1835 | `endif | |
1836 | pci_am5 <= `PCI_AM5; //FR2201 pci_am0 | |
1837 | pci_ta5 <= `PCI_TA5 ;//FR2201 translation address ; | |
1838 | `endif | |
1839 | /*pci_err_cs_bit31_24 ; pci_err_cs_bit10; pci_err_cs_bit9 ; pci_err_cs_bit8 ;*/ pci_err_cs_bit0 <= 1'h0 ; | |
1840 | /*pci_err_addr ;*/ | |
1841 | /*pci_err_data ;*/ | |
1842 | // | |
1843 | wb_img_ctrl1_bit2_0 <= {`WB_AT_EN1, 2'b00} ; | |
1844 | ||
1845 | wb_ba1_bit31_12 <=`WB_BA1; //FR2201 Address bar | |
1846 | wb_ba1_bit0 <=`WB_BA1_MEM_IO;// | |
1847 | wb_am1 <= `WB_AM1 ;//FR2201 Address mask | |
1848 | wb_ta1 <= `WB_TA1 ;//FR2201 20'h0000_0 ; | |
1849 | `ifdef WB_IMAGE2 | |
1850 | wb_img_ctrl2_bit2_0 <= {`WB_AT_EN2, 2'b00} ; | |
1851 | ||
1852 | wb_ba2_bit31_12 <=`WB_BA2; //FR2201 Address bar | |
1853 | wb_ba2_bit0 <=`WB_BA2_MEM_IO;// | |
1854 | wb_am2 <=`WB_AM2 ;//FR2201 Address mask | |
1855 | wb_ta2 <=`WB_TA2 ;//FR2201 translation address ; | |
1856 | `endif | |
1857 | `ifdef WB_IMAGE3 | |
1858 | wb_img_ctrl3_bit2_0 <= {`WB_AT_EN3, 2'b00} ; | |
1859 | ||
1860 | wb_ba3_bit31_12 <=`WB_BA3; //FR2201 Address bar | |
1861 | wb_ba3_bit0 <=`WB_BA3_MEM_IO;// | |
1862 | wb_am3 <=`WB_AM3 ;//FR2201 Address mask | |
1863 | wb_ta3 <=`WB_TA3 ;//FR2201 translation address ; | |
1864 | `endif | |
1865 | `ifdef WB_IMAGE4 | |
1866 | wb_img_ctrl4_bit2_0 <= {`WB_AT_EN4, 2'b00} ; | |
1867 | ||
1868 | wb_ba4_bit31_12 <=`WB_BA4; //FR2201 Address bar | |
1869 | wb_ba4_bit0 <=`WB_BA4_MEM_IO;// | |
1870 | wb_am4 <=`WB_AM4 ;//FR2201 Address mask | |
1871 | wb_ta4 <=`WB_TA4 ;//FR2201 translation address ; | |
1872 | `endif | |
1873 | `ifdef WB_IMAGE5 | |
1874 | wb_img_ctrl5_bit2_0 <= {`WB_AT_EN5, 2'b00} ; | |
1875 | ||
1876 | wb_ba5_bit31_12 <=`WB_BA5; //FR2201 Address bar ; | |
1877 | wb_ba5_bit0 <=`WB_BA5_MEM_IO;//FR2201 1'h0 ; | |
1878 | wb_am5 <=`WB_AM5 ;//FR2201 Address mask | |
1879 | wb_ta5 <=`WB_TA5 ;//FR2201 translation address ; | |
1880 | `endif | |
1881 | /*wb_err_cs_bit31_24 ; wb_err_cs_bit10 ; wb_err_cs_bit9 ; wb_err_cs_bit8 ;*/ wb_err_cs_bit0 <= 1'h0 ; | |
1882 | /*wb_err_addr ;*/ | |
1883 | /*wb_err_data ;*/ | |
1884 | ||
1885 | `ifdef HOST | |
1886 | cnf_addr_bit23_2 <= 22'h0000_00 ; cnf_addr_bit0 <= 1'h0 ; | |
1887 | `endif | |
1888 | ||
1889 | icr_bit31 <= 1'h0 ; | |
1890 | `ifdef HOST | |
1891 | icr_bit2_0 <= 3'h0 ; | |
1892 | icr_bit4_3 <= 2'h0 ; | |
1893 | `else | |
1894 | icr_bit2_0[2:0] <= 3'h0 ; | |
1895 | `endif | |
1896 | /*isr_bit4_3 ; isr_bit2_0 ;*/ | |
1897 | ||
1898 | // Not register bit; used only internally after reset! | |
1899 | init_complete <= 1'b0 ; | |
1900 | ||
1901 | `ifdef GUEST | |
1902 | rst_inactive_sync <= 1'b0 ; | |
1903 | rst_inactive <= 1'b0 ; | |
1904 | `endif | |
1905 | ||
1906 | `ifdef PCI_CPCI_HS_IMPLEMENT | |
1907 | /*hs_ins hs_ext*/ hs_loo <= 1'b0; hs_eim <= 1'b0; | |
1908 | // Not register bits; used only internally after reset! | |
1909 | /*hs_ins_armed hs_ext_armed*/ | |
1910 | `endif | |
1911 | end | |
1912 | /* ----------------------------------------------------------------------------------------------------------- | |
1913 | Following register bits should have asynchronous RESET & SET! That is why they are IMPLEMENTED separately | |
1914 | after this ALWAYS block!!! (for every register bit, there are two D-FF implemented) | |
1915 | status_bit15_11[15] <= 1'b1 ; | |
1916 | status_bit15_11[14] <= 1'b1 ; | |
1917 | status_bit15_11[13] <= 1'b1 ; | |
1918 | status_bit15_11[12] <= 1'b1 ; | |
1919 | status_bit15_11[11] <= 1'b1 ; | |
1920 | status_bit8 <= 1'b1 ; | |
1921 | pci_err_cs_bit10 <= 1'b1 ; | |
1922 | pci_err_cs_bit9 <= 1'b1 ; | |
1923 | pci_err_cs_bit8 <= 1'b1 ; | |
1924 | pci_err_cs_bit31_24 <= { pci_error_be, pci_error_bc } ; | |
1925 | pci_err_addr <= pci_error_addr ; | |
1926 | pci_err_data <= pci_error_data ; | |
1927 | wb_err_cs_bit10 <= 1'b1 ; | |
1928 | wb_err_cs_bit9 <= 1'b1 ; | |
1929 | wb_err_cs_bit8 <= 1'b1 ; | |
1930 | wb_err_cs_bit31_24 <= { wb_error_be, wb_error_bc } ; | |
1931 | wb_err_addr <= wb_error_addr ; | |
1932 | wb_err_data <= wb_error_data ; | |
1933 | isr_bit4_0[4] <= 1'b1 & icr_bit4_0[4] ; | |
1934 | isr_bit4_0[3] <= 1'b1 & icr_bit4_0[3] ; | |
1935 | isr_bit4_0[2] <= 1'b1 & icr_bit4_0[2] ; | |
1936 | isr_bit4_0[1] <= 1'b1 & icr_bit4_0[1] ; | |
1937 | isr_bit4_0[0] <= 1'b1 & icr_bit4_0[0] ; | |
1938 | ||
1939 | hs_ins; hs_ext; | |
1940 | -----------------------------------------------------------------------------------------------------------*/ | |
1941 | // Here follows normal writting to registers (only to their valid bits) ! | |
1942 | else | |
1943 | begin | |
1944 | if (w_we) | |
1945 | begin | |
1946 | // PCI header - configuration space | |
1947 | if (w_reg_select_dec[0]) // w_conf_address[5:2] = 4'h1: | |
1948 | begin | |
1949 | if (~w_byte_en[1]) | |
1950 | command_bit8 <= w_conf_data[8] ; | |
1951 | if (~w_byte_en[0]) | |
1952 | begin | |
1953 | command_bit6 <= w_conf_data[6] ; | |
1954 | command_bit2_0 <= w_conf_data[2:0] ; | |
1955 | end | |
1956 | end | |
1957 | if (w_reg_select_dec[1]) // w_conf_address[5:2] = 4'h3: | |
1958 | begin | |
1959 | if (~w_byte_en[1]) | |
1960 | latency_timer <= w_conf_data[15:8] ; | |
1961 | if (~w_byte_en[0]) | |
1962 | cache_line_size_reg <= w_conf_data[7:0] ; | |
1963 | end | |
1964 | // if (w_reg_select_dec[4]) // w_conf_address[5:2] = 4'h4: | |
1965 | // Also used with IMAGE0 | |
1966 | ||
1967 | // if (w_reg_select_dec[8]) // w_conf_address[5:2] = 4'h5: | |
1968 | // Also used with IMAGE1 | |
1969 | ||
1970 | // if (w_reg_select_dec[12]) // w_conf_address[5:2] = 4'h6: | |
1971 | // Also used with IMAGE2 | |
1972 | ||
1973 | // if (w_reg_select_dec[16]) // w_conf_address[5:2] = 4'h7: | |
1974 | // Also used with IMAGE3 | |
1975 | ||
1976 | // if (w_reg_select_dec[20]) // w_conf_address[5:2] = 4'h8: | |
1977 | // Also used with IMAGE4 | |
1978 | ||
1979 | // if (w_reg_select_dec[24]) // w_conf_address[5:2] = 4'h9: | |
1980 | // Also used with IMAGE5 and IMAGE6 | |
1981 | if (w_reg_select_dec[2]) // w_conf_address[5:2] = 4'hf: | |
1982 | begin | |
1983 | if (~w_byte_en[0]) | |
1984 | interrupt_line <= w_conf_data[7:0] ; | |
1985 | end | |
1986 | // PCI target - configuration space | |
1987 | `ifdef HOST | |
1988 | `ifdef NO_CNF_IMAGE | |
1989 | `ifdef PCI_IMAGE0 // if PCI bridge is HOST and IMAGE0 is assigned as general image space | |
1990 | if (w_reg_select_dec[3]) // case (w_conf_address[7:2]) = `P_IMG_CTRL0_ADDR: | |
1991 | begin | |
1992 | if (~w_byte_en[0]) | |
1993 | pci_img_ctrl0_bit2_1 <= w_conf_data[2:1] ; | |
1994 | end | |
1995 | if (w_reg_select_dec[4]) // case (w_conf_address[7:2]) = `P_BA0_ADDR: | |
1996 | begin | |
1997 | if (~w_byte_en[3]) | |
1998 | pci_ba0_bit31_8[31:24] <= w_conf_pdata_reduced[31:24] ; | |
1999 | if (~w_byte_en[2]) | |
2000 | pci_ba0_bit31_8[23:16] <= w_conf_pdata_reduced[23:16] ; | |
2001 | if (~w_byte_en[1]) | |
2002 | pci_ba0_bit31_8[15: 8] <= w_conf_pdata_reduced[15: 8] ; | |
2003 | if (~w_byte_en[0]) | |
2004 | pci_ba0_bit0 <= w_conf_data[0] ; | |
2005 | end | |
2006 | if (w_reg_select_dec[5]) // case (w_conf_address[7:2]) = `P_AM0_ADDR: | |
2007 | begin | |
2008 | if (~w_byte_en[3]) | |
2009 | pci_am0[31:24] <= w_conf_pdata_reduced[31:24] ; | |
2010 | if (~w_byte_en[2]) | |
2011 | pci_am0[23:16] <= w_conf_pdata_reduced[23:16] ; | |
2012 | if (~w_byte_en[1]) | |
2013 | pci_am0[15: 8] <= w_conf_pdata_reduced[15: 8] ; | |
2014 | end | |
2015 | if (w_reg_select_dec[6]) // case (w_conf_address[7:2]) = `P_TA0_ADDR: | |
2016 | begin | |
2017 | if (~w_byte_en[3]) | |
2018 | pci_ta0[31:24] <= w_conf_pdata_reduced[31:24] ; | |
2019 | if (~w_byte_en[2]) | |
2020 | pci_ta0[23:16] <= w_conf_pdata_reduced[23:16] ; | |
2021 | if (~w_byte_en[1]) | |
2022 | pci_ta0[15: 8] <= w_conf_pdata_reduced[15: 8] ; | |
2023 | end | |
2024 | `endif | |
2025 | `else | |
2026 | if (w_reg_select_dec[4]) // case (w_conf_address[7:2]) = `P_BA0_ADDR: | |
2027 | begin | |
2028 | if (~w_byte_en[3]) | |
2029 | pci_ba0_bit31_8[31:24] <= w_conf_data[31:24] ; | |
2030 | if (~w_byte_en[2]) | |
2031 | pci_ba0_bit31_8[23:16] <= w_conf_data[23:16] ; | |
2032 | if (~w_byte_en[1]) | |
2033 | pci_ba0_bit31_8[15:12] <= w_conf_data[15:12] ; | |
2034 | end | |
2035 | `endif | |
2036 | `endif | |
2037 | ||
2038 | `ifdef GUEST | |
2039 | if (w_reg_select_dec[4]) // case (w_conf_address[7:2]) = `P_BA0_ADDR: | |
2040 | begin | |
2041 | if (~w_byte_en[3]) | |
2042 | pci_ba0_bit31_8[31:24] <= w_conf_data[31:24] ; | |
2043 | if (~w_byte_en[2]) | |
2044 | pci_ba0_bit31_8[23:16] <= w_conf_data[23:16] ; | |
2045 | if (~w_byte_en[1]) | |
2046 | pci_ba0_bit31_8[15:12] <= w_conf_data[15:12] ; | |
2047 | end | |
2048 | `endif | |
2049 | if (w_reg_select_dec[7]) // case (w_conf_address[7:2]) = `P_IMG_CTRL1_ADDR: | |
2050 | begin | |
2051 | if (~w_byte_en[0]) | |
2052 | pci_img_ctrl1_bit2_1 <= w_conf_data[2:1] ; | |
2053 | end | |
2054 | if (w_reg_select_dec[8]) // case (w_conf_address[7:2]) = `P_BA1_ADDR: | |
2055 | begin | |
2056 | if (~w_byte_en[3]) | |
2057 | pci_ba1_bit31_8[31:24] <= w_conf_pdata_reduced[31:24] ; | |
2058 | if (~w_byte_en[2]) | |
2059 | pci_ba1_bit31_8[23:16] <= w_conf_pdata_reduced[23:16] ; | |
2060 | if (~w_byte_en[1]) | |
2061 | pci_ba1_bit31_8[15: 8] <= w_conf_pdata_reduced[15: 8] ; | |
2062 | `ifdef HOST | |
2063 | if (~w_byte_en[0]) | |
2064 | pci_ba1_bit0 <= w_conf_data[0] ; | |
2065 | `endif | |
2066 | end | |
2067 | if (w_reg_select_dec[9]) // case (w_conf_address[7:2]) = `P_AM1_ADDR: | |
2068 | begin | |
2069 | if (~w_byte_en[3]) | |
2070 | pci_am1[31:24] <= w_conf_pdata_reduced[31:24] ; | |
2071 | if (~w_byte_en[2]) | |
2072 | pci_am1[23:16] <= w_conf_pdata_reduced[23:16] ; | |
2073 | if (~w_byte_en[1]) | |
2074 | pci_am1[15: 8] <= w_conf_pdata_reduced[15: 8] ; | |
2075 | end | |
2076 | if (w_reg_select_dec[10]) // case (w_conf_address[7:2]) = `P_TA1_ADDR: | |
2077 | begin | |
2078 | if (~w_byte_en[3]) | |
2079 | pci_ta1[31:24] <= w_conf_pdata_reduced[31:24] ; | |
2080 | if (~w_byte_en[2]) | |
2081 | pci_ta1[23:16] <= w_conf_pdata_reduced[23:16] ; | |
2082 | if (~w_byte_en[1]) | |
2083 | pci_ta1[15: 8] <= w_conf_pdata_reduced[15: 8] ; | |
2084 | end | |
2085 | `ifdef PCI_IMAGE2 | |
2086 | if (w_reg_select_dec[11]) // case (w_conf_address[7:2]) = `P_IMG_CTRL2_ADDR: | |
2087 | begin | |
2088 | if (~w_byte_en[0]) | |
2089 | pci_img_ctrl2_bit2_1 <= w_conf_data[2:1] ; | |
2090 | end | |
2091 | if (w_reg_select_dec[12]) // case (w_conf_address[7:2]) = `P_BA2_ADDR: | |
2092 | begin | |
2093 | if (~w_byte_en[3]) | |
2094 | pci_ba2_bit31_8[31:24] <= w_conf_pdata_reduced[31:24] ; | |
2095 | if (~w_byte_en[2]) | |
2096 | pci_ba2_bit31_8[23:16] <= w_conf_pdata_reduced[23:16] ; | |
2097 | if (~w_byte_en[1]) | |
2098 | pci_ba2_bit31_8[15: 8] <= w_conf_pdata_reduced[15: 8] ; | |
2099 | `ifdef HOST | |
2100 | if (~w_byte_en[0]) | |
2101 | pci_ba2_bit0 <= w_conf_data[0] ; | |
2102 | `endif | |
2103 | end | |
2104 | if (w_reg_select_dec[13]) // case (w_conf_address[7:2]) = `P_AM2_ADDR: | |
2105 | begin | |
2106 | if (~w_byte_en[3]) | |
2107 | pci_am2[31:24] <= w_conf_pdata_reduced[31:24] ; | |
2108 | if (~w_byte_en[2]) | |
2109 | pci_am2[23:16] <= w_conf_pdata_reduced[23:16] ; | |
2110 | if (~w_byte_en[1]) | |
2111 | pci_am2[15: 8] <= w_conf_pdata_reduced[15: 8] ; | |
2112 | end | |
2113 | if (w_reg_select_dec[14]) // case (w_conf_address[7:2]) = `P_TA2_ADDR: | |
2114 | begin | |
2115 | if (~w_byte_en[3]) | |
2116 | pci_ta2[31:24] <= w_conf_pdata_reduced[31:24] ; | |
2117 | if (~w_byte_en[2]) | |
2118 | pci_ta2[23:16] <= w_conf_pdata_reduced[23:16] ; | |
2119 | if (~w_byte_en[1]) | |
2120 | pci_ta2[15: 8] <= w_conf_pdata_reduced[15: 8] ; | |
2121 | end | |
2122 | `endif | |
2123 | `ifdef PCI_IMAGE3 | |
2124 | if (w_reg_select_dec[15]) // case (w_conf_address[7:2]) = `P_IMG_CTRL3_ADDR: | |
2125 | begin | |
2126 | if (~w_byte_en[0]) | |
2127 | pci_img_ctrl3_bit2_1 <= w_conf_data[2:1] ; | |
2128 | end | |
2129 | if (w_reg_select_dec[16]) // case (w_conf_address[7:2]) = `P_BA3_ADDR: | |
2130 | begin | |
2131 | if (~w_byte_en[3]) | |
2132 | pci_ba3_bit31_8[31:24] <= w_conf_pdata_reduced[31:24] ; | |
2133 | if (~w_byte_en[2]) | |
2134 | pci_ba3_bit31_8[23:16] <= w_conf_pdata_reduced[23:16] ; | |
2135 | if (~w_byte_en[1]) | |
2136 | pci_ba3_bit31_8[15: 8] <= w_conf_pdata_reduced[15: 8] ; | |
2137 | `ifdef HOST | |
2138 | if (~w_byte_en[0]) | |
2139 | pci_ba3_bit0 <= w_conf_data[0] ; | |
2140 | `endif | |
2141 | end | |
2142 | if (w_reg_select_dec[17]) // case (w_conf_address[7:2]) = `P_AM3_ADDR: | |
2143 | begin | |
2144 | if (~w_byte_en[3]) | |
2145 | pci_am3[31:24] <= w_conf_pdata_reduced[31:24] ; | |
2146 | if (~w_byte_en[2]) | |
2147 | pci_am3[23:16] <= w_conf_pdata_reduced[23:16] ; | |
2148 | if (~w_byte_en[1]) | |
2149 | pci_am3[15: 8] <= w_conf_pdata_reduced[15: 8] ; | |
2150 | end | |
2151 | if (w_reg_select_dec[18]) // case (w_conf_address[7:2]) = `P_TA3_ADDR: | |
2152 | begin | |
2153 | if (~w_byte_en[3]) | |
2154 | pci_ta3[31:24] <= w_conf_pdata_reduced[31:24] ; | |
2155 | if (~w_byte_en[2]) | |
2156 | pci_ta3[23:16] <= w_conf_pdata_reduced[23:16] ; | |
2157 | if (~w_byte_en[1]) | |
2158 | pci_ta3[15: 8] <= w_conf_pdata_reduced[15: 8] ; | |
2159 | end | |
2160 | `endif | |
2161 | `ifdef PCI_IMAGE4 | |
2162 | if (w_reg_select_dec[19]) // case (w_conf_address[7:2]) = `P_IMG_CTRL4_ADDR: | |
2163 | begin | |
2164 | if (~w_byte_en[0]) | |
2165 | pci_img_ctrl4_bit2_1 <= w_conf_data[2:1] ; | |
2166 | end | |
2167 | if (w_reg_select_dec[20]) // case (w_conf_address[7:2]) = `P_BA4_ADDR: | |
2168 | begin | |
2169 | if (~w_byte_en[3]) | |
2170 | pci_ba4_bit31_8[31:24] <= w_conf_pdata_reduced[31:24] ; | |
2171 | if (~w_byte_en[2]) | |
2172 | pci_ba4_bit31_8[23:16] <= w_conf_pdata_reduced[23:16] ; | |
2173 | if (~w_byte_en[1]) | |
2174 | pci_ba4_bit31_8[15: 8] <= w_conf_pdata_reduced[15: 8] ; | |
2175 | `ifdef HOST | |
2176 | if (~w_byte_en[0]) | |
2177 | pci_ba4_bit0 <= w_conf_data[0] ; | |
2178 | `endif | |
2179 | end | |
2180 | if (w_reg_select_dec[21]) // case (w_conf_address[7:2]) = `P_AM4_ADDR: | |
2181 | begin | |
2182 | if (~w_byte_en[3]) | |
2183 | pci_am4[31:24] <= w_conf_pdata_reduced[31:24] ; | |
2184 | if (~w_byte_en[2]) | |
2185 | pci_am4[23:16] <= w_conf_pdata_reduced[23:16] ; | |
2186 | if (~w_byte_en[1]) | |
2187 | pci_am4[15: 8] <= w_conf_pdata_reduced[15: 8] ; | |
2188 | end | |
2189 | if (w_reg_select_dec[22]) // case (w_conf_address[7:2]) = `P_TA4_ADDR: | |
2190 | begin | |
2191 | if (~w_byte_en[3]) | |
2192 | pci_ta4[31:24] <= w_conf_pdata_reduced[31:24] ; | |
2193 | if (~w_byte_en[2]) | |
2194 | pci_ta4[23:16] <= w_conf_pdata_reduced[23:16] ; | |
2195 | if (~w_byte_en[1]) | |
2196 | pci_ta4[15: 8] <= w_conf_pdata_reduced[15: 8] ; | |
2197 | end | |
2198 | `endif | |
2199 | `ifdef PCI_IMAGE5 | |
2200 | if (w_reg_select_dec[23]) // case (w_conf_address[7:2]) = `P_IMG_CTRL5_ADDR: | |
2201 | begin | |
2202 | if (~w_byte_en[0]) | |
2203 | pci_img_ctrl5_bit2_1 <= w_conf_data[2:1] ; | |
2204 | end | |
2205 | if (w_reg_select_dec[24]) // case (w_conf_address[7:2]) = `P_BA5_ADDR: | |
2206 | begin | |
2207 | if (~w_byte_en[3]) | |
2208 | pci_ba5_bit31_8[31:24] <= w_conf_pdata_reduced[31:24] ; | |
2209 | if (~w_byte_en[2]) | |
2210 | pci_ba5_bit31_8[23:16] <= w_conf_pdata_reduced[23:16] ; | |
2211 | if (~w_byte_en[1]) | |
2212 | pci_ba5_bit31_8[15: 8] <= w_conf_pdata_reduced[15: 8] ; | |
2213 | `ifdef HOST | |
2214 | if (~w_byte_en[0]) | |
2215 | pci_ba5_bit0 <= w_conf_data[0] ; | |
2216 | `endif | |
2217 | end | |
2218 | if (w_reg_select_dec[25]) // case (w_conf_address[7:2]) = `P_AM5_ADDR: | |
2219 | begin | |
2220 | if (~w_byte_en[3]) | |
2221 | pci_am5[31:24] <= w_conf_pdata_reduced[31:24] ; | |
2222 | if (~w_byte_en[2]) | |
2223 | pci_am5[23:16] <= w_conf_pdata_reduced[23:16] ; | |
2224 | if (~w_byte_en[1]) | |
2225 | pci_am5[15: 8] <= w_conf_pdata_reduced[15: 8] ; | |
2226 | end | |
2227 | if (w_reg_select_dec[26]) // case (w_conf_address[7:2]) = `P_TA5_ADDR: | |
2228 | begin | |
2229 | if (~w_byte_en[3]) | |
2230 | pci_ta5[31:24] <= w_conf_pdata_reduced[31:24] ; | |
2231 | if (~w_byte_en[2]) | |
2232 | pci_ta5[23:16] <= w_conf_pdata_reduced[23:16] ; | |
2233 | if (~w_byte_en[1]) | |
2234 | pci_ta5[15: 8] <= w_conf_pdata_reduced[15: 8] ; | |
2235 | end | |
2236 | `endif | |
2237 | if (w_reg_select_dec[27]) // case (w_conf_address[7:2]) = `P_ERR_CS_ADDR: | |
2238 | begin | |
2239 | if (~w_byte_en[0]) | |
2240 | pci_err_cs_bit0 <= w_conf_data[0] ; | |
2241 | end | |
2242 | // WB slave - configuration space | |
2243 | if (w_reg_select_dec[30]) // case (w_conf_address[7:2]) = `W_IMG_CTRL1_ADDR: | |
2244 | begin | |
2245 | if (~w_byte_en[0]) | |
2246 | wb_img_ctrl1_bit2_0 <= w_conf_data[2:0] ; | |
2247 | end | |
2248 | if (w_reg_select_dec[31]) // case (w_conf_address[7:2]) = `W_BA1_ADDR: | |
2249 | begin | |
2250 | if (~w_byte_en[3]) | |
2251 | wb_ba1_bit31_12[31:24] <= w_conf_wdata_reduced[31:24] ; | |
2252 | if (~w_byte_en[2]) | |
2253 | wb_ba1_bit31_12[23:16] <= w_conf_wdata_reduced[23:16] ; | |
2254 | if (~w_byte_en[1]) | |
2255 | wb_ba1_bit31_12[15:12] <= w_conf_wdata_reduced[15:12] ; | |
2256 | if (~w_byte_en[0]) | |
2257 | wb_ba1_bit0 <= w_conf_data[0] ; | |
2258 | end | |
2259 | if (w_reg_select_dec[32]) // case (w_conf_address[7:2]) = `W_AM1_ADDR: | |
2260 | begin | |
2261 | if (~w_byte_en[3]) | |
2262 | wb_am1[31:24] <= w_conf_wdata_reduced[31:24] ; | |
2263 | if (~w_byte_en[2]) | |
2264 | wb_am1[23:16] <= w_conf_wdata_reduced[23:16] ; | |
2265 | if (~w_byte_en[1]) | |
2266 | wb_am1[15:12] <= w_conf_wdata_reduced[15:12] ; | |
2267 | end | |
2268 | if (w_reg_select_dec[33]) // case (w_conf_address[7:2]) = `W_TA1_ADDR: | |
2269 | begin | |
2270 | if (~w_byte_en[3]) | |
2271 | wb_ta1[31:24] <= w_conf_wdata_reduced[31:24] ; | |
2272 | if (~w_byte_en[2]) | |
2273 | wb_ta1[23:16] <= w_conf_wdata_reduced[23:16] ; | |
2274 | if (~w_byte_en[1]) | |
2275 | wb_ta1[15:12] <= w_conf_wdata_reduced[15:12] ; | |
2276 | end | |
2277 | `ifdef WB_IMAGE2 | |
2278 | if (w_reg_select_dec[34]) // case (w_conf_address[7:2]) = `W_IMG_CTRL2_ADDR: | |
2279 | begin | |
2280 | if (~w_byte_en[0]) | |
2281 | wb_img_ctrl2_bit2_0 <= w_conf_data[2:0] ; | |
2282 | end | |
2283 | if (w_reg_select_dec[35]) // case (w_conf_address[7:2]) = `W_BA2_ADDR: | |
2284 | begin | |
2285 | if (~w_byte_en[3]) | |
2286 | wb_ba2_bit31_12[31:24] <= w_conf_wdata_reduced[31:24] ; | |
2287 | if (~w_byte_en[2]) | |
2288 | wb_ba2_bit31_12[23:16] <= w_conf_wdata_reduced[23:16] ; | |
2289 | if (~w_byte_en[1]) | |
2290 | wb_ba2_bit31_12[15:12] <= w_conf_wdata_reduced[15:12] ; | |
2291 | if (~w_byte_en[0]) | |
2292 | wb_ba2_bit0 <= w_conf_data[0] ; | |
2293 | end | |
2294 | if (w_reg_select_dec[36]) // case (w_conf_address[7:2]) = `W_AM2_ADDR: | |
2295 | begin | |
2296 | if (~w_byte_en[3]) | |
2297 | wb_am2[31:24] <= w_conf_wdata_reduced[31:24] ; | |
2298 | if (~w_byte_en[2]) | |
2299 | wb_am2[23:16] <= w_conf_wdata_reduced[23:16] ; | |
2300 | if (~w_byte_en[1]) | |
2301 | wb_am2[15:12] <= w_conf_wdata_reduced[15:12] ; | |
2302 | end | |
2303 | if (w_reg_select_dec[37]) // case (w_conf_address[7:2]) = `W_TA2_ADDR: | |
2304 | begin | |
2305 | if (~w_byte_en[3]) | |
2306 | wb_ta2[31:24] <= w_conf_wdata_reduced[31:24] ; | |
2307 | if (~w_byte_en[2]) | |
2308 | wb_ta2[23:16] <= w_conf_wdata_reduced[23:16] ; | |
2309 | if (~w_byte_en[1]) | |
2310 | wb_ta2[15:12] <= w_conf_wdata_reduced[15:12] ; | |
2311 | end | |
2312 | `endif | |
2313 | `ifdef WB_IMAGE3 | |
2314 | if (w_reg_select_dec[38]) // case (w_conf_address[7:2]) = `W_IMG_CTRL3_ADDR: | |
2315 | begin | |
2316 | if (~w_byte_en[0]) | |
2317 | wb_img_ctrl3_bit2_0 <= w_conf_data[2:0] ; | |
2318 | end | |
2319 | if (w_reg_select_dec[39]) // case (w_conf_address[7:2]) = `W_BA3_ADDR: | |
2320 | begin | |
2321 | if (~w_byte_en[3]) | |
2322 | wb_ba3_bit31_12[31:24] <= w_conf_wdata_reduced[31:24] ; | |
2323 | if (~w_byte_en[2]) | |
2324 | wb_ba3_bit31_12[23:16] <= w_conf_wdata_reduced[23:16] ; | |
2325 | if (~w_byte_en[1]) | |
2326 | wb_ba3_bit31_12[15:12] <= w_conf_wdata_reduced[15:12] ; | |
2327 | if (~w_byte_en[0]) | |
2328 | wb_ba3_bit0 <= w_conf_data[0] ; | |
2329 | end | |
2330 | if (w_reg_select_dec[40]) // case (w_conf_address[7:2]) = `W_AM3_ADDR: | |
2331 | begin | |
2332 | if (~w_byte_en[3]) | |
2333 | wb_am3[31:24] <= w_conf_wdata_reduced[31:24] ; | |
2334 | if (~w_byte_en[2]) | |
2335 | wb_am3[23:16] <= w_conf_wdata_reduced[23:16] ; | |
2336 | if (~w_byte_en[1]) | |
2337 | wb_am3[15:12] <= w_conf_wdata_reduced[15:12] ; | |
2338 | end | |
2339 | if (w_reg_select_dec[41]) // case (w_conf_address[7:2]) = `W_TA3_ADDR: | |
2340 | begin | |
2341 | if (~w_byte_en[3]) | |
2342 | wb_ta3[31:24] <= w_conf_wdata_reduced[31:24] ; | |
2343 | if (~w_byte_en[2]) | |
2344 | wb_ta3[23:16] <= w_conf_wdata_reduced[23:16] ; | |
2345 | if (~w_byte_en[1]) | |
2346 | wb_ta3[15:12] <= w_conf_wdata_reduced[15:12] ; | |
2347 | end | |
2348 | `endif | |
2349 | `ifdef WB_IMAGE4 | |
2350 | if (w_reg_select_dec[42]) // case (w_conf_address[7:2]) = `W_IMG_CTRL4_ADDR: | |
2351 | begin | |
2352 | if (~w_byte_en[0]) | |
2353 | wb_img_ctrl4_bit2_0 <= w_conf_data[2:0] ; | |
2354 | end | |
2355 | if (w_reg_select_dec[43]) // case (w_conf_address[7:2]) = `W_BA4_ADDR: | |
2356 | begin | |
2357 | if (~w_byte_en[3]) | |
2358 | wb_ba4_bit31_12[31:24] <= w_conf_wdata_reduced[31:24] ; | |
2359 | if (~w_byte_en[2]) | |
2360 | wb_ba4_bit31_12[23:16] <= w_conf_wdata_reduced[23:16] ; | |
2361 | if (~w_byte_en[1]) | |
2362 | wb_ba4_bit31_12[15:12] <= w_conf_wdata_reduced[15:12] ; | |
2363 | if (~w_byte_en[0]) | |
2364 | wb_ba4_bit0 <= w_conf_data[0] ; | |
2365 | end | |
2366 | if (w_reg_select_dec[44]) // case (w_conf_address[7:2]) = `W_AM4_ADDR: | |
2367 | begin | |
2368 | if (~w_byte_en[3]) | |
2369 | wb_am4[31:24] <= w_conf_wdata_reduced[31:24] ; | |
2370 | if (~w_byte_en[2]) | |
2371 | wb_am4[23:16] <= w_conf_wdata_reduced[23:16] ; | |
2372 | if (~w_byte_en[1]) | |
2373 | wb_am4[15:12] <= w_conf_wdata_reduced[15:12] ; | |
2374 | end | |
2375 | if (w_reg_select_dec[45]) // case (w_conf_address[7:2]) = `W_TA4_ADDR: | |
2376 | begin | |
2377 | if (~w_byte_en[3]) | |
2378 | wb_ta4[31:24] <= w_conf_wdata_reduced[31:24] ; | |
2379 | if (~w_byte_en[2]) | |
2380 | wb_ta4[23:16] <= w_conf_wdata_reduced[23:16] ; | |
2381 | if (~w_byte_en[1]) | |
2382 | wb_ta4[15:12] <= w_conf_wdata_reduced[15:12] ; | |
2383 | end | |
2384 | `endif | |
2385 | `ifdef WB_IMAGE5 | |
2386 | if (w_reg_select_dec[46]) // case (w_conf_address[7:2]) = `W_IMG_CTRL5_ADDR: | |
2387 | begin | |
2388 | if (~w_byte_en[0]) | |
2389 | wb_img_ctrl5_bit2_0 <= w_conf_data[2:0] ; | |
2390 | end | |
2391 | if (w_reg_select_dec[47]) // case (w_conf_address[7:2]) = `W_BA5_ADDR: | |
2392 | begin | |
2393 | if (~w_byte_en[3]) | |
2394 | wb_ba5_bit31_12[31:24] <= w_conf_wdata_reduced[31:24] ; | |
2395 | if (~w_byte_en[2]) | |
2396 | wb_ba5_bit31_12[23:16] <= w_conf_wdata_reduced[23:16] ; | |
2397 | if (~w_byte_en[1]) | |
2398 | wb_ba5_bit31_12[15:12] <= w_conf_wdata_reduced[15:12] ; | |
2399 | if (~w_byte_en[0]) | |
2400 | wb_ba5_bit0 <= w_conf_data[0] ; | |
2401 | end | |
2402 | if (w_reg_select_dec[48]) // case (w_conf_address[7:2]) = `W_AM5_ADDR: | |
2403 | begin | |
2404 | if (~w_byte_en[3]) | |
2405 | wb_am5[31:24] <= w_conf_wdata_reduced[31:24] ; | |
2406 | if (~w_byte_en[2]) | |
2407 | wb_am5[23:16] <= w_conf_wdata_reduced[23:16] ; | |
2408 | if (~w_byte_en[1]) | |
2409 | wb_am5[15:12] <= w_conf_wdata_reduced[15:12] ; | |
2410 | end | |
2411 | if (w_reg_select_dec[49]) // case (w_conf_address[7:2]) = `W_TA5_ADDR: | |
2412 | begin | |
2413 | if (~w_byte_en[3]) | |
2414 | wb_ta5[31:24] <= w_conf_wdata_reduced[31:24] ; | |
2415 | if (~w_byte_en[2]) | |
2416 | wb_ta5[23:16] <= w_conf_wdata_reduced[23:16] ; | |
2417 | if (~w_byte_en[1]) | |
2418 | wb_ta5[15:12] <= w_conf_wdata_reduced[15:12] ; | |
2419 | end | |
2420 | `endif | |
2421 | if (w_reg_select_dec[50]) // case (w_conf_address[7:2]) = `W_ERR_CS_ADDR: | |
2422 | begin | |
2423 | if (~w_byte_en[0]) | |
2424 | wb_err_cs_bit0 <= w_conf_data[0] ; | |
2425 | end | |
2426 | ||
2427 | `ifdef HOST | |
2428 | if (w_reg_select_dec[53]) // case (w_conf_address[7:2]) = `CNF_ADDR_ADDR: | |
2429 | begin | |
2430 | if (~w_byte_en[2]) | |
2431 | cnf_addr_bit23_2[23:16] <= w_conf_data[23:16] ; | |
2432 | if (~w_byte_en[1]) | |
2433 | cnf_addr_bit23_2[15:8] <= w_conf_data[15:8] ; | |
2434 | if (~w_byte_en[0]) | |
2435 | begin | |
2436 | cnf_addr_bit23_2[7:2] <= w_conf_data[7:2] ; | |
2437 | cnf_addr_bit0 <= w_conf_data[0] ; | |
2438 | end | |
2439 | end | |
2440 | `endif | |
2441 | // `CNF_DATA_ADDR: implemented elsewhere !!! | |
2442 | // `INT_ACK_ADDR : implemented elsewhere !!! | |
2443 | if (w_reg_select_dec[54]) // case (w_conf_address[7:2]) = `ICR_ADDR: | |
2444 | begin | |
2445 | if (~w_byte_en[3]) | |
2446 | icr_bit31 <= w_conf_data[31] ; | |
2447 | ||
2448 | if (~w_byte_en[0]) | |
2449 | begin | |
2450 | `ifdef HOST | |
2451 | icr_bit4_3 <= w_conf_data[4:3] ; | |
2452 | icr_bit2_0 <= w_conf_data[2:0] ; | |
2453 | `else | |
2454 | icr_bit2_0[2:0] <= w_conf_data[2:0] ; | |
2455 | `endif | |
2456 | end | |
2457 | end | |
2458 | ||
2459 | `ifdef PCI_CPCI_HS_IMPLEMENT | |
2460 | if (w_reg_select_dec[56]) | |
2461 | begin | |
2462 | if (~w_byte_en[2]) | |
2463 | begin | |
2464 | hs_loo <= w_conf_data[19]; | |
2465 | hs_eim <= w_conf_data[17]; | |
2466 | end | |
2467 | end | |
2468 | `endif | |
2469 | end // end of we | |
2470 | ||
2471 | // Not register bits; used only internally after reset! | |
2472 | `ifdef GUEST | |
2473 | rst_inactive_sync <= 1'b1 ; | |
2474 | rst_inactive <= rst_inactive_sync ; | |
2475 | `endif | |
2476 | ||
2477 | if (rst_inactive & ~init_complete & init_cfg_done) | |
2478 | init_complete <= 1'b1 ; | |
2479 | end | |
2480 | end | |
2481 | ||
2482 | // implementation of read only device identification registers | |
2483 | always@(posedge w_clock or posedge reset) | |
2484 | begin | |
2485 | if (reset) | |
2486 | begin | |
2487 | r_vendor_id <= `HEADER_VENDOR_ID ; | |
2488 | r_device_id <= `HEADER_DEVICE_ID ; | |
2489 | r_revision_id <= `HEADER_REVISION_ID ; | |
2490 | r_subsys_vendor_id <= `HEADER_SUBSYS_VENDOR_ID ; | |
2491 | r_subsys_id <= `HEADER_SUBSYS_ID ; | |
2492 | r_max_lat <= `HEADER_MAX_LAT ; | |
2493 | r_min_gnt <= `HEADER_MIN_GNT ; | |
2494 | end else | |
2495 | begin | |
2496 | if (init_we) | |
2497 | begin | |
2498 | if (spoci_reg_num == 'h0) | |
2499 | begin | |
2500 | r_vendor_id <= spoci_dat[15: 0] ; | |
2501 | r_device_id <= spoci_dat[31:16] ; | |
2502 | end | |
2503 | ||
2504 | if (spoci_reg_num == 'hB) | |
2505 | begin | |
2506 | r_subsys_vendor_id <= spoci_dat[15: 0] ; | |
2507 | r_subsys_id <= spoci_dat[31:16] ; | |
2508 | end | |
2509 | ||
2510 | if (spoci_reg_num == 'h2) | |
2511 | begin | |
2512 | r_revision_id <= spoci_dat[ 7: 0] ; | |
2513 | end | |
2514 | ||
2515 | if (spoci_reg_num == 'hF) | |
2516 | begin | |
2517 | r_max_lat <= spoci_dat[31:24] ; | |
2518 | r_min_gnt <= spoci_dat[23:16] ; | |
2519 | end | |
2520 | end | |
2521 | end | |
2522 | end | |
2523 | ||
2524 | // This signals are synchronous resets for registers, whic occures when asynchronous RESET is '1' or | |
2525 | // data '1' is synchronously written into them! | |
2526 | reg delete_status_bit15 ; | |
2527 | reg delete_status_bit14 ; | |
2528 | reg delete_status_bit13 ; | |
2529 | reg delete_status_bit12 ; | |
2530 | reg delete_status_bit11 ; | |
2531 | reg delete_status_bit8 ; | |
2532 | reg delete_pci_err_cs_bit8 ; | |
2533 | reg delete_wb_err_cs_bit8 ; | |
2534 | reg delete_isr_bit4 ; | |
2535 | reg delete_isr_bit3 ; | |
2536 | reg delete_isr_bit2 ; | |
2537 | reg delete_isr_bit1 ; | |
2538 | ||
2539 | // This are aditional register bits, which are resets when their value is '1' !!! | |
2540 | always@(w_we or w_reg_select_dec or w_conf_data or w_byte_en) | |
2541 | begin | |
2542 | // I' is written into, then it also sets signals to '1' | |
2543 | delete_status_bit15 = w_conf_data[31] & !w_byte_en[3] & w_we & w_reg_select_dec[0] ; | |
2544 | delete_status_bit14 = w_conf_data[30] & !w_byte_en[3] & w_we & w_reg_select_dec[0] ; | |
2545 | delete_status_bit13 = w_conf_data[29] & !w_byte_en[3] & w_we & w_reg_select_dec[0] ; | |
2546 | delete_status_bit12 = w_conf_data[28] & !w_byte_en[3] & w_we & w_reg_select_dec[0] ; | |
2547 | delete_status_bit11 = w_conf_data[27] & !w_byte_en[3] & w_we & w_reg_select_dec[0] ; | |
2548 | delete_status_bit8 = w_conf_data[24] & !w_byte_en[3] & w_we & w_reg_select_dec[0] ; | |
2549 | delete_pci_err_cs_bit8 = w_conf_data[8] & !w_byte_en[1] & w_we & w_reg_select_dec[27] ; | |
2550 | delete_wb_err_cs_bit8 = w_conf_data[8] & !w_byte_en[1] & w_we & w_reg_select_dec[50] ; | |
2551 | delete_isr_bit4 = w_conf_data[4] & !w_byte_en[0] & w_we & w_reg_select_dec[55] ; | |
2552 | delete_isr_bit3 = w_conf_data[3] & !w_byte_en[0] & w_we & w_reg_select_dec[55] ; | |
2553 | delete_isr_bit2 = w_conf_data[2] & !w_byte_en[0] & w_we & w_reg_select_dec[55] ; | |
2554 | delete_isr_bit1 = w_conf_data[1] & !w_byte_en[0] & w_we & w_reg_select_dec[55] ; | |
2555 | end | |
2556 | ||
2557 | // STATUS BITS of PCI Header status register | |
2558 | `ifdef SYNCHRONEOUS_CLOCK_DOMAINS | |
2559 | // Set and clear FF | |
2560 | always@(posedge pci_clk or posedge reset) | |
2561 | begin | |
2562 | if (reset) // Asynchronous reset | |
2563 | status_bit15_11[15] <= 1'b0 ; | |
2564 | else | |
2565 | begin | |
2566 | if (perr_in) // Synchronous set | |
2567 | status_bit15_11[15] <= 1'b1 ; | |
2568 | else if (delete_status_bit15) // Synchronous reset | |
2569 | status_bit15_11[15] <= 1'b0 ; | |
2570 | end | |
2571 | end | |
2572 | // Set and clear FF | |
2573 | always@(posedge pci_clk or posedge reset) | |
2574 | begin | |
2575 | if (reset) // Asynchronous reset | |
2576 | status_bit15_11[14] <= 1'b0 ; | |
2577 | else | |
2578 | begin | |
2579 | if (serr_in) // Synchronous set | |
2580 | status_bit15_11[14] <= 1'b1 ; | |
2581 | else if (delete_status_bit14) // Synchronous reset | |
2582 | status_bit15_11[14] <= 1'b0 ; | |
2583 | end | |
2584 | end | |
2585 | // Set and clear FF | |
2586 | always@(posedge pci_clk or posedge reset) | |
2587 | begin | |
2588 | if (reset) // Asynchronous reset | |
2589 | status_bit15_11[13] <= 1'b0 ; | |
2590 | else | |
2591 | begin | |
2592 | if (master_abort_recv) // Synchronous set | |
2593 | status_bit15_11[13] <= 1'b1 ; | |
2594 | else if (delete_status_bit13) // Synchronous reset | |
2595 | status_bit15_11[13] <= 1'b0 ; | |
2596 | end | |
2597 | end | |
2598 | // Set and clear FF | |
2599 | always@(posedge pci_clk or posedge reset) | |
2600 | begin | |
2601 | if (reset) // Asynchronous reset | |
2602 | status_bit15_11[12] <= 1'b0 ; | |
2603 | else | |
2604 | begin | |
2605 | if (target_abort_recv) // Synchronous set | |
2606 | status_bit15_11[12] <= 1'b1 ; | |
2607 | else if (delete_status_bit12) // Synchronous reset | |
2608 | status_bit15_11[12] <= 1'b0 ; | |
2609 | end | |
2610 | end | |
2611 | // Set and clear FF | |
2612 | always@(posedge pci_clk or posedge reset) | |
2613 | begin | |
2614 | if (reset) // Asynchronous reset | |
2615 | status_bit15_11[11] <= 1'b0 ; | |
2616 | else | |
2617 | begin | |
2618 | if (target_abort_set) // Synchronous set | |
2619 | status_bit15_11[11] <= 1'b1 ; | |
2620 | else if (delete_status_bit11) // Synchronous reset | |
2621 | status_bit15_11[11] <= 1'b0 ; | |
2622 | end | |
2623 | end | |
2624 | // Set and clear FF | |
2625 | always@(posedge pci_clk or posedge reset) | |
2626 | begin | |
2627 | if (reset) // Asynchronous reset | |
2628 | status_bit8 <= 1'b0 ; | |
2629 | else | |
2630 | begin | |
2631 | if (master_data_par_err) // Synchronous set | |
2632 | status_bit8 <= 1'b1 ; | |
2633 | else if (delete_status_bit8) // Synchronous reset | |
2634 | status_bit8 <= 1'b0 ; | |
2635 | end | |
2636 | end | |
2637 | `else // not SYNCHRONEOUS_CLOCK_DOMAINS | |
2638 | `ifdef HOST | |
2639 | reg [15:11] set_status_bit15_11; | |
2640 | reg set_status_bit8; | |
2641 | wire delete_set_status_bit15; | |
2642 | wire delete_set_status_bit14; | |
2643 | wire delete_set_status_bit13; | |
2644 | wire delete_set_status_bit12; | |
2645 | wire delete_set_status_bit11; | |
2646 | wire delete_set_status_bit8; | |
2647 | wire block_set_status_bit15; | |
2648 | wire block_set_status_bit14; | |
2649 | wire block_set_status_bit13; | |
2650 | wire block_set_status_bit12; | |
2651 | wire block_set_status_bit11; | |
2652 | wire block_set_status_bit8; | |
2653 | // Synchronization module for clearing FF between two clock domains | |
2654 | pci_sync_module sync_status_15 | |
2655 | ( | |
2656 | .set_clk_in (pci_clk), | |
2657 | .delete_clk_in (wb_clk), | |
2658 | .reset_in (reset), | |
2659 | .delete_set_out (delete_set_status_bit15), | |
2660 | .block_set_out (block_set_status_bit15), | |
2661 | .delete_in (delete_status_bit15) | |
2662 | ); | |
2663 | // Setting FF | |
2664 | always@(posedge pci_clk or posedge reset) | |
2665 | begin | |
2666 | if (reset) // Asynchronous reset | |
2667 | set_status_bit15_11[15] <= 1'b0 ; | |
2668 | else | |
2669 | begin | |
2670 | if (perr_in) // Synchronous set | |
2671 | set_status_bit15_11[15] <= 1'b1 ; | |
2672 | else if (delete_set_status_bit15) // Synchronous reset | |
2673 | set_status_bit15_11[15] <= 1'b0 ; | |
2674 | end | |
2675 | end | |
2676 | // Synchronization module for clearing FF between two clock domains | |
2677 | pci_sync_module sync_status_14 | |
2678 | ( | |
2679 | .set_clk_in (pci_clk), | |
2680 | .delete_clk_in (wb_clk), | |
2681 | .reset_in (reset), | |
2682 | .delete_set_out (delete_set_status_bit14), | |
2683 | .block_set_out (block_set_status_bit14), | |
2684 | .delete_in (delete_status_bit14) | |
2685 | ); | |
2686 | // Setting FF | |
2687 | always@(posedge pci_clk or posedge reset) | |
2688 | begin | |
2689 | if (reset) // Asynchronous reset | |
2690 | set_status_bit15_11[14] <= 1'b0 ; | |
2691 | else | |
2692 | begin | |
2693 | if (serr_in) // Synchronous set | |
2694 | set_status_bit15_11[14] <= 1'b1 ; | |
2695 | else if (delete_set_status_bit14) // Synchronous reset | |
2696 | set_status_bit15_11[14] <= 1'b0 ; | |
2697 | end | |
2698 | end | |
2699 | // Synchronization module for clearing FF between two clock domains | |
2700 | pci_sync_module sync_status_13 | |
2701 | ( | |
2702 | .set_clk_in (pci_clk), | |
2703 | .delete_clk_in (wb_clk), | |
2704 | .reset_in (reset), | |
2705 | .delete_set_out (delete_set_status_bit13), | |
2706 | .block_set_out (block_set_status_bit13), | |
2707 | .delete_in (delete_status_bit13) | |
2708 | ); | |
2709 | // Setting FF | |
2710 | always@(posedge pci_clk or posedge reset) | |
2711 | begin | |
2712 | if (reset) // Asynchronous reset | |
2713 | set_status_bit15_11[13] <= 1'b0 ; | |
2714 | else | |
2715 | begin | |
2716 | if (master_abort_recv) // Synchronous set | |
2717 | set_status_bit15_11[13] <= 1'b1 ; | |
2718 | else if (delete_set_status_bit13) // Synchronous reset | |
2719 | set_status_bit15_11[13] <= 1'b0 ; | |
2720 | end | |
2721 | end | |
2722 | // Synchronization module for clearing FF between two clock domains | |
2723 | pci_sync_module sync_status_12 | |
2724 | ( | |
2725 | .set_clk_in (pci_clk), | |
2726 | .delete_clk_in (wb_clk), | |
2727 | .reset_in (reset), | |
2728 | .delete_set_out (delete_set_status_bit12), | |
2729 | .block_set_out (block_set_status_bit12), | |
2730 | .delete_in (delete_status_bit12) | |
2731 | ); | |
2732 | // Setting FF | |
2733 | always@(posedge pci_clk or posedge reset) | |
2734 | begin | |
2735 | if (reset) // Asynchronous reset | |
2736 | set_status_bit15_11[12] <= 1'b0 ; | |
2737 | else | |
2738 | begin | |
2739 | if (target_abort_recv) // Synchronous set | |
2740 | set_status_bit15_11[12] <= 1'b1 ; | |
2741 | else if (delete_set_status_bit12) // Synchronous reset | |
2742 | set_status_bit15_11[12] <= 1'b0 ; | |
2743 | end | |
2744 | end | |
2745 | // Synchronization module for clearing FF between two clock domains | |
2746 | pci_sync_module sync_status_11 | |
2747 | ( | |
2748 | .set_clk_in (pci_clk), | |
2749 | .delete_clk_in (wb_clk), | |
2750 | .reset_in (reset), | |
2751 | .delete_set_out (delete_set_status_bit11), | |
2752 | .block_set_out (block_set_status_bit11), | |
2753 | .delete_in (delete_status_bit11) | |
2754 | ); | |
2755 | // Setting FF | |
2756 | always@(posedge pci_clk or posedge reset) | |
2757 | begin | |
2758 | if (reset) // Asynchronous reset | |
2759 | set_status_bit15_11[11] <= 1'b0 ; | |
2760 | else | |
2761 | begin | |
2762 | if (target_abort_set) // Synchronous set | |
2763 | set_status_bit15_11[11] <= 1'b1 ; | |
2764 | else if (delete_set_status_bit11) // Synchronous reset | |
2765 | set_status_bit15_11[11] <= 1'b0 ; | |
2766 | end | |
2767 | end | |
2768 | // Synchronization module for clearing FF between two clock domains | |
2769 | pci_sync_module sync_status_8 | |
2770 | ( | |
2771 | .set_clk_in (pci_clk), | |
2772 | .delete_clk_in (wb_clk), | |
2773 | .reset_in (reset), | |
2774 | .delete_set_out (delete_set_status_bit8), | |
2775 | .block_set_out (block_set_status_bit8), | |
2776 | .delete_in (delete_status_bit8) | |
2777 | ); | |
2778 | // Setting FF | |
2779 | always@(posedge pci_clk or posedge reset) | |
2780 | begin | |
2781 | if (reset) // Asynchronous reset | |
2782 | set_status_bit8 <= 1'b0 ; | |
2783 | else | |
2784 | begin | |
2785 | if (master_data_par_err) // Synchronous set | |
2786 | set_status_bit8 <= 1'b1 ; | |
2787 | else if (delete_set_status_bit8) // Synchronous reset | |
2788 | set_status_bit8 <= 1'b0 ; | |
2789 | end | |
2790 | end | |
2791 | wire [5:0] status_bits = {set_status_bit15_11[15] && !block_set_status_bit15, | |
2792 | set_status_bit15_11[14] && !block_set_status_bit14, | |
2793 | set_status_bit15_11[13] && !block_set_status_bit13, | |
2794 | set_status_bit15_11[12] && !block_set_status_bit12, | |
2795 | set_status_bit15_11[11] && !block_set_status_bit11, | |
2796 | set_status_bit8 && !block_set_status_bit8 } ; | |
2797 | wire [5:0] meta_status_bits ; | |
2798 | // interemediate stage to clk synchronization flip - flops - this ones are prone to metastability | |
2799 | pci_synchronizer_flop #(6, 0) status_bits_sync | |
2800 | ( | |
2801 | .data_in (status_bits), | |
2802 | .clk_out (wb_clk), | |
2803 | .sync_data_out (meta_status_bits), | |
2804 | .async_reset (reset) | |
2805 | ) ; | |
2806 | always@(posedge wb_clk or posedge reset) | |
2807 | begin | |
2808 | if (reset) | |
2809 | begin | |
2810 | status_bit15_11[15:11] <= 5'b0 ; | |
2811 | status_bit8 <= 1'b0 ; | |
2812 | end | |
2813 | else | |
2814 | begin | |
2815 | status_bit15_11[15:11] <= meta_status_bits[5:1] ; | |
2816 | status_bit8 <= meta_status_bits[0] ; | |
2817 | end | |
2818 | end | |
2819 | `else // GUEST | |
2820 | // Set and clear FF | |
2821 | always@(posedge pci_clk or posedge reset) | |
2822 | begin | |
2823 | if (reset) // Asynchronous reset | |
2824 | status_bit15_11[15] <= 1'b0 ; | |
2825 | else | |
2826 | begin | |
2827 | if (perr_in) // Synchronous set | |
2828 | status_bit15_11[15] <= 1'b1 ; | |
2829 | else if (delete_status_bit15) // Synchronous reset | |
2830 | status_bit15_11[15] <= 1'b0 ; | |
2831 | end | |
2832 | end | |
2833 | // Set and clear FF | |
2834 | always@(posedge pci_clk or posedge reset) | |
2835 | begin | |
2836 | if (reset) // Asynchronous reset | |
2837 | status_bit15_11[14] <= 1'b0 ; | |
2838 | else | |
2839 | begin | |
2840 | if (serr_in) // Synchronous set | |
2841 | status_bit15_11[14] <= 1'b1 ; | |
2842 | else if (delete_status_bit14) // Synchronous reset | |
2843 | status_bit15_11[14] <= 1'b0 ; | |
2844 | end | |
2845 | end | |
2846 | // Set and clear FF | |
2847 | always@(posedge pci_clk or posedge reset) | |
2848 | begin | |
2849 | if (reset) // Asynchronous reset | |
2850 | status_bit15_11[13] <= 1'b0 ; | |
2851 | else | |
2852 | begin | |
2853 | if (master_abort_recv) // Synchronous set | |
2854 | status_bit15_11[13] <= 1'b1 ; | |
2855 | else if (delete_status_bit13) // Synchronous reset | |
2856 | status_bit15_11[13] <= 1'b0 ; | |
2857 | end | |
2858 | end | |
2859 | // Set and clear FF | |
2860 | always@(posedge pci_clk or posedge reset) | |
2861 | begin | |
2862 | if (reset) // Asynchronous reset | |
2863 | status_bit15_11[12] <= 1'b0 ; | |
2864 | else | |
2865 | begin | |
2866 | if (target_abort_recv) // Synchronous set | |
2867 | status_bit15_11[12] <= 1'b1 ; | |
2868 | else if (delete_status_bit12) // Synchronous reset | |
2869 | status_bit15_11[12] <= 1'b0 ; | |
2870 | end | |
2871 | end | |
2872 | // Set and clear FF | |
2873 | always@(posedge pci_clk or posedge reset) | |
2874 | begin | |
2875 | if (reset) // Asynchronous reset | |
2876 | status_bit15_11[11] <= 1'b0 ; | |
2877 | else | |
2878 | begin | |
2879 | if (target_abort_set) // Synchronous set | |
2880 | status_bit15_11[11] <= 1'b1 ; | |
2881 | else if (delete_status_bit11) // Synchronous reset | |
2882 | status_bit15_11[11] <= 1'b0 ; | |
2883 | end | |
2884 | end | |
2885 | // Set and clear FF | |
2886 | always@(posedge pci_clk or posedge reset) | |
2887 | begin | |
2888 | if (reset) // Asynchronous reset | |
2889 | status_bit8 <= 1'b0 ; | |
2890 | else | |
2891 | begin | |
2892 | if (master_data_par_err) // Synchronous set | |
2893 | status_bit8 <= 1'b1 ; | |
2894 | else if (delete_status_bit8) // Synchronous reset | |
2895 | status_bit8 <= 1'b0 ; | |
2896 | end | |
2897 | end | |
2898 | `endif | |
2899 | `endif | |
2900 | ||
2901 | // STATUS BITS of P_ERR_CS - PCI error control and status register | |
2902 | `ifdef SYNCHRONEOUS_CLOCK_DOMAINS | |
2903 | // Set and clear FF | |
2904 | always@(posedge pci_clk or posedge reset) | |
2905 | begin | |
2906 | if (reset) // Asynchronous reset | |
2907 | pci_err_cs_bit8 <= 1'b0 ; | |
2908 | else | |
2909 | begin | |
2910 | if (pci_error_sig && pci_err_cs_bit0) // Synchronous set | |
2911 | pci_err_cs_bit8 <= 1'b1 ; | |
2912 | else if (delete_pci_err_cs_bit8) // Synchronous reset | |
2913 | pci_err_cs_bit8 <= 1'b0 ; | |
2914 | end | |
2915 | end | |
2916 | `else // not SYNCHRONEOUS_CLOCK_DOMAINS | |
2917 | `ifdef HOST | |
2918 | // Set and clear FF | |
2919 | always@(posedge wb_clk or posedge reset) | |
2920 | begin | |
2921 | if (reset) // Asynchronous reset | |
2922 | pci_err_cs_bit8 <= 1'b0 ; | |
2923 | else | |
2924 | begin | |
2925 | if (pci_error_sig && pci_err_cs_bit0) // Synchronous set | |
2926 | pci_err_cs_bit8 <= 1'b1 ; | |
2927 | else if (delete_pci_err_cs_bit8) // Synchronous reset | |
2928 | pci_err_cs_bit8 <= 1'b0 ; | |
2929 | end | |
2930 | end | |
2931 | `else // GUEST | |
2932 | reg set_pci_err_cs_bit8; | |
2933 | wire delete_set_pci_err_cs_bit8; | |
2934 | wire block_set_pci_err_cs_bit8; | |
2935 | // Synchronization module for clearing FF between two clock domains | |
2936 | pci_sync_module sync_pci_err_cs_8 | |
2937 | ( | |
2938 | .set_clk_in (wb_clk), | |
2939 | .delete_clk_in (pci_clk), | |
2940 | .reset_in (reset), | |
2941 | .delete_set_out (delete_set_pci_err_cs_bit8), | |
2942 | .block_set_out (block_set_pci_err_cs_bit8), | |
2943 | .delete_in (delete_pci_err_cs_bit8) | |
2944 | ); | |
2945 | // Setting FF | |
2946 | always@(posedge wb_clk or posedge reset) | |
2947 | begin | |
2948 | if (reset) // Asynchronous reset | |
2949 | set_pci_err_cs_bit8 <= 1'b0 ; | |
2950 | else | |
2951 | begin | |
2952 | if (pci_error_sig && pci_err_cs_bit0) // Synchronous set | |
2953 | set_pci_err_cs_bit8 <= 1'b1 ; | |
2954 | else if (delete_set_pci_err_cs_bit8) // Synchronous reset | |
2955 | set_pci_err_cs_bit8 <= 1'b0 ; | |
2956 | end | |
2957 | end | |
2958 | wire pci_err_cs_bits = set_pci_err_cs_bit8 && !block_set_pci_err_cs_bit8 ; | |
2959 | wire meta_pci_err_cs_bits ; | |
2960 | // interemediate stage to clk synchronization flip - flops - this ones are prone to metastability | |
2961 | pci_synchronizer_flop #(1,0) pci_err_cs_bits_sync | |
2962 | ( | |
2963 | .data_in (pci_err_cs_bits), | |
2964 | .clk_out (pci_clk), | |
2965 | .sync_data_out (meta_pci_err_cs_bits), | |
2966 | .async_reset (reset) | |
2967 | ) ; | |
2968 | always@(posedge pci_clk or posedge reset) | |
2969 | begin | |
2970 | if (reset) | |
2971 | pci_err_cs_bit8 <= 1'b0 ; | |
2972 | else | |
2973 | pci_err_cs_bit8 <= meta_pci_err_cs_bits ; | |
2974 | end | |
2975 | `endif | |
2976 | `endif | |
2977 | // Set and clear FF | |
2978 | always@(posedge wb_clk or posedge reset) | |
2979 | begin | |
2980 | if (reset) // Asynchronous reset | |
2981 | pci_err_cs_bit10 <= 1'b0 ; | |
2982 | else | |
2983 | begin | |
2984 | if (pci_error_sig) // Synchronous report | |
2985 | pci_err_cs_bit10 <= pci_error_rty_exp ; | |
2986 | end | |
2987 | end | |
2988 | // Set and clear FF | |
2989 | always@(posedge wb_clk or posedge reset) | |
2990 | begin | |
2991 | if (reset) // Asynchronous reset | |
2992 | pci_err_cs_bit9 <= 1'b0 ; | |
2993 | else | |
2994 | begin | |
2995 | if (pci_error_sig) // Synchronous report | |
2996 | pci_err_cs_bit9 <= pci_error_es ; | |
2997 | end | |
2998 | end | |
2999 | // Set and clear FF | |
3000 | always@(posedge wb_clk or posedge reset) | |
3001 | begin | |
3002 | if (reset) // Asynchronous reset | |
3003 | begin | |
3004 | pci_err_cs_bit31_24 <= 8'h00 ; | |
3005 | pci_err_addr <= 32'h0000_0000 ; | |
3006 | pci_err_data <= 32'h0000_0000 ; | |
3007 | end | |
3008 | else | |
3009 | if (pci_error_sig) // Synchronous report | |
3010 | begin | |
3011 | pci_err_cs_bit31_24 <= { pci_error_be, pci_error_bc } ; | |
3012 | pci_err_addr <= pci_error_addr ; | |
3013 | pci_err_data <= pci_error_data ; | |
3014 | end | |
3015 | end | |
3016 | ||
3017 | // STATUS BITS of W_ERR_CS - WB error control and status register | |
3018 | `ifdef SYNCHRONEOUS_CLOCK_DOMAINS | |
3019 | // Set and clear FF | |
3020 | always@(posedge pci_clk or posedge reset) | |
3021 | begin | |
3022 | if (reset) // Asynchronous reset | |
3023 | wb_err_cs_bit8 <= 1'b0 ; | |
3024 | else | |
3025 | begin | |
3026 | if (wb_error_sig && wb_err_cs_bit0) // Synchronous set | |
3027 | wb_err_cs_bit8 <= 1'b1 ; | |
3028 | else if (delete_wb_err_cs_bit8) // Synchronous reset | |
3029 | wb_err_cs_bit8 <= 1'b0 ; | |
3030 | end | |
3031 | end | |
3032 | `else // not SYNCHRONEOUS_CLOCK_DOMAINS | |
3033 | `ifdef HOST | |
3034 | reg set_wb_err_cs_bit8; | |
3035 | wire delete_set_wb_err_cs_bit8; | |
3036 | wire block_set_wb_err_cs_bit8; | |
3037 | // Synchronization module for clearing FF between two clock domains | |
3038 | pci_sync_module sync_wb_err_cs_8 | |
3039 | ( | |
3040 | .set_clk_in (pci_clk), | |
3041 | .delete_clk_in (wb_clk), | |
3042 | .reset_in (reset), | |
3043 | .delete_set_out (delete_set_wb_err_cs_bit8), | |
3044 | .block_set_out (block_set_wb_err_cs_bit8), | |
3045 | .delete_in (delete_wb_err_cs_bit8) | |
3046 | ); | |
3047 | // Setting FF | |
3048 | always@(posedge pci_clk or posedge reset) | |
3049 | begin | |
3050 | if (reset) // Asynchronous reset | |
3051 | set_wb_err_cs_bit8 <= 1'b0 ; | |
3052 | else | |
3053 | begin | |
3054 | if (wb_error_sig && wb_err_cs_bit0) // Synchronous set | |
3055 | set_wb_err_cs_bit8 <= 1'b1 ; | |
3056 | else if (delete_set_wb_err_cs_bit8) // Synchronous reset | |
3057 | set_wb_err_cs_bit8 <= 1'b0 ; | |
3058 | end | |
3059 | end | |
3060 | wire wb_err_cs_bits = set_wb_err_cs_bit8 && !block_set_wb_err_cs_bit8 ; | |
3061 | wire meta_wb_err_cs_bits ; | |
3062 | // interemediate stage to clk synchronization flip - flops - this ones are prone to metastability | |
3063 | pci_synchronizer_flop #(1,0) wb_err_cs_bits_sync | |
3064 | ( | |
3065 | .data_in (wb_err_cs_bits), | |
3066 | .clk_out (wb_clk), | |
3067 | .sync_data_out (meta_wb_err_cs_bits), | |
3068 | .async_reset (reset) | |
3069 | ) ; | |
3070 | always@(posedge wb_clk or posedge reset) | |
3071 | begin | |
3072 | if (reset) | |
3073 | wb_err_cs_bit8 <= 1'b0 ; | |
3074 | else | |
3075 | wb_err_cs_bit8 <= meta_wb_err_cs_bits ; | |
3076 | end | |
3077 | `else // GUEST | |
3078 | // Set and clear FF | |
3079 | always@(posedge pci_clk or posedge reset) | |
3080 | begin | |
3081 | if (reset) // Asynchronous reset | |
3082 | wb_err_cs_bit8 <= 1'b0 ; | |
3083 | else | |
3084 | begin | |
3085 | if (wb_error_sig && wb_err_cs_bit0) // Synchronous set | |
3086 | wb_err_cs_bit8 <= 1'b1 ; | |
3087 | else if (delete_wb_err_cs_bit8) // Synchronous reset | |
3088 | wb_err_cs_bit8 <= 1'b0 ; | |
3089 | end | |
3090 | end | |
3091 | `endif | |
3092 | `endif | |
3093 | /* // Set and clear FF | |
3094 | always@(posedge pci_clk or posedge reset) | |
3095 | begin | |
3096 | if (reset) // Asynchronous reset | |
3097 | wb_err_cs_bit10 <= 1'b0 ; | |
3098 | else | |
3099 | begin | |
3100 | if (wb_error_sig) // Synchronous report | |
3101 | wb_err_cs_bit10 <= wb_error_rty_exp ; | |
3102 | end | |
3103 | end */ | |
3104 | // Set and clear FF | |
3105 | always@(posedge pci_clk or posedge reset) | |
3106 | begin | |
3107 | if (reset) // Asynchronous reset | |
3108 | wb_err_cs_bit9 <= 1'b0 ; | |
3109 | else | |
3110 | begin | |
3111 | if (wb_error_sig) // Synchronous report | |
3112 | wb_err_cs_bit9 <= wb_error_es ; | |
3113 | end | |
3114 | end | |
3115 | // Set and clear FF | |
3116 | always@(posedge pci_clk or posedge reset) | |
3117 | begin | |
3118 | if (reset) // Asynchronous reset | |
3119 | begin | |
3120 | wb_err_cs_bit31_24 <= 8'h00 ; | |
3121 | wb_err_addr <= 32'h0000_0000 ; | |
3122 | wb_err_data <= 32'h0000_0000 ; | |
3123 | end | |
3124 | else | |
3125 | if (wb_error_sig) | |
3126 | begin | |
3127 | wb_err_cs_bit31_24 <= { wb_error_be, wb_error_bc } ; | |
3128 | wb_err_addr <= wb_error_addr ; | |
3129 | wb_err_data <= wb_error_data ; | |
3130 | end | |
3131 | end | |
3132 | ||
3133 | // SERR_INT and PERR_INT STATUS BITS of ISR - interrupt status register | |
3134 | `ifdef SYNCHRONEOUS_CLOCK_DOMAINS | |
3135 | `ifdef HOST | |
3136 | // Set and clear FF | |
3137 | always@(posedge pci_clk or posedge reset) | |
3138 | begin | |
3139 | if (reset) // Asynchronous reset | |
3140 | isr_bit4_3[4] <= 1'b0 ; | |
3141 | else | |
3142 | begin | |
3143 | if (isr_sys_err_int && icr_bit4_3[4]) // Synchronous set | |
3144 | isr_bit4_3[4] <= 1'b1 ; | |
3145 | else if (delete_isr_bit4) // Synchronous reset | |
3146 | isr_bit4_3[4] <= 1'b0 ; | |
3147 | end | |
3148 | end | |
3149 | // Set and clear FF | |
3150 | always@(posedge pci_clk or posedge reset) | |
3151 | begin | |
3152 | if (reset) // Asynchronous reset | |
3153 | isr_bit4_3[3] <= 1'b0 ; | |
3154 | else | |
3155 | begin | |
3156 | if (isr_par_err_int && icr_bit4_3[3]) // Synchronous set | |
3157 | isr_bit4_3[3] <= 1'b1 ; | |
3158 | else if (delete_isr_bit3) // Synchronous reset | |
3159 | isr_bit4_3[3] <= 1'b0 ; | |
3160 | end | |
3161 | end | |
3162 | `endif | |
3163 | `else // not SYNCHRONEOUS_CLOCK_DOMAINS | |
3164 | `ifdef HOST | |
3165 | reg [4:3] set_isr_bit4_3; | |
3166 | wire delete_set_isr_bit4; | |
3167 | wire delete_set_isr_bit3; | |
3168 | wire block_set_isr_bit4; | |
3169 | wire block_set_isr_bit3; | |
3170 | // Synchronization module for clearing FF between two clock domains | |
3171 | pci_sync_module sync_isr_4 | |
3172 | ( | |
3173 | .set_clk_in (pci_clk), | |
3174 | .delete_clk_in (wb_clk), | |
3175 | .reset_in (reset), | |
3176 | .delete_set_out (delete_set_isr_bit4), | |
3177 | .block_set_out (block_set_isr_bit4), | |
3178 | .delete_in (delete_isr_bit4) | |
3179 | ); | |
3180 | // Setting FF | |
3181 | always@(posedge pci_clk or posedge reset) | |
3182 | begin | |
3183 | if (reset) // Asynchronous reset | |
3184 | set_isr_bit4_3[4] <= 1'b0 ; | |
3185 | else | |
3186 | begin | |
3187 | if (isr_sys_err_int && icr_bit4_3[4]) // Synchronous set | |
3188 | set_isr_bit4_3[4] <= 1'b1 ; | |
3189 | else if (delete_set_isr_bit4) // Synchronous reset | |
3190 | set_isr_bit4_3[4] <= 1'b0 ; | |
3191 | end | |
3192 | end | |
3193 | // Synchronization module for clearing FF between two clock domains | |
3194 | pci_sync_module sync_isr_3 | |
3195 | ( | |
3196 | .set_clk_in (pci_clk), | |
3197 | .delete_clk_in (wb_clk), | |
3198 | .reset_in (reset), | |
3199 | .delete_set_out (delete_set_isr_bit3), | |
3200 | .block_set_out (block_set_isr_bit3), | |
3201 | .delete_in (delete_isr_bit3) | |
3202 | ); | |
3203 | // Setting FF | |
3204 | always@(posedge pci_clk or posedge reset) | |
3205 | begin | |
3206 | if (reset) // Asynchronous reset | |
3207 | set_isr_bit4_3[3] <= 1'b0 ; | |
3208 | else | |
3209 | begin | |
3210 | if (isr_par_err_int && icr_bit4_3[3]) // Synchronous set | |
3211 | set_isr_bit4_3[3] <= 1'b1 ; | |
3212 | else if (delete_set_isr_bit3) // Synchronous reset | |
3213 | set_isr_bit4_3[3] <= 1'b0 ; | |
3214 | end | |
3215 | end | |
3216 | wire [4:3] isr_bits4_3 = {set_isr_bit4_3[4] && !block_set_isr_bit4, | |
3217 | set_isr_bit4_3[3] && !block_set_isr_bit3 } ; | |
3218 | wire [4:3] meta_isr_bits4_3 ; | |
3219 | // interemediate stage to clk synchronization flip - flops - this ones are prone to metastability | |
3220 | pci_synchronizer_flop #(2, 0) isr_bits_sync | |
3221 | ( | |
3222 | .data_in (isr_bits4_3), | |
3223 | .clk_out (wb_clk), | |
3224 | .sync_data_out (meta_isr_bits4_3), | |
3225 | .async_reset (reset) | |
3226 | ) ; | |
3227 | always@(posedge wb_clk or posedge reset) | |
3228 | begin | |
3229 | if (reset) | |
3230 | isr_bit4_3[4:3] <= 2'b0 ; | |
3231 | else | |
3232 | isr_bit4_3[4:3] <= meta_isr_bits4_3[4:3] ; | |
3233 | end | |
3234 | `endif | |
3235 | `endif | |
3236 | ||
3237 | // PCI_EINT and WB_EINT STATUS BITS of ISR - interrupt status register | |
3238 | `ifdef SYNCHRONEOUS_CLOCK_DOMAINS | |
3239 | // WB_EINT STATUS BIT | |
3240 | // Set and clear FF | |
3241 | always@(posedge pci_clk or posedge reset) | |
3242 | begin | |
3243 | if (reset) // Asynchronous reset | |
3244 | isr_bit2_0[1] <= 1'b0 ; | |
3245 | else | |
3246 | begin | |
3247 | if (wb_error_sig && icr_bit2_0[1] && wb_err_cs_bit0) // Synchronous set | |
3248 | isr_bit2_0[1] <= 1'b1 ; | |
3249 | else if (delete_isr_bit1) // Synchronous reset | |
3250 | isr_bit2_0[1] <= 1'b0 ; | |
3251 | end | |
3252 | end | |
3253 | // PCI_EINT STATUS BIT | |
3254 | // Set and clear FF | |
3255 | always@(posedge pci_clk or posedge reset) | |
3256 | begin | |
3257 | if (reset) // Asynchronous reset | |
3258 | isr_bit2_0[2] <= 1'b0 ; | |
3259 | else | |
3260 | begin | |
3261 | if (pci_error_sig && icr_bit2_0[2] && pci_err_cs_bit0) // Synchronous set | |
3262 | isr_bit2_0[2] <= 1'b1 ; | |
3263 | else if (delete_isr_bit2) // Synchronous reset | |
3264 | isr_bit2_0[2] <= 1'b0 ; | |
3265 | end | |
3266 | end | |
3267 | `else // not SYNCHRONEOUS_CLOCK_DOMAINS | |
3268 | `ifdef HOST | |
3269 | // WB_EINT STATUS BIT | |
3270 | reg set_isr_bit1; | |
3271 | wire delete_set_isr_bit1; | |
3272 | wire block_set_isr_bit1; | |
3273 | // Synchronization module for clearing FF between two clock domains | |
3274 | pci_sync_module sync_isr_1 | |
3275 | ( | |
3276 | .set_clk_in (pci_clk), | |
3277 | .delete_clk_in (wb_clk), | |
3278 | .reset_in (reset), | |
3279 | .delete_set_out (delete_set_isr_bit1), | |
3280 | .block_set_out (block_set_isr_bit1), | |
3281 | .delete_in (delete_isr_bit1) | |
3282 | ); | |
3283 | // Setting FF | |
3284 | always@(posedge pci_clk or posedge reset) | |
3285 | begin | |
3286 | if (reset) // Asynchronous reset | |
3287 | set_isr_bit1 <= 1'b0 ; | |
3288 | else | |
3289 | begin | |
3290 | if (wb_error_sig && icr_bit2_0[1] && wb_err_cs_bit0) // Synchronous set | |
3291 | set_isr_bit1 <= 1'b1 ; | |
3292 | else if (delete_set_isr_bit1) // Synchronous reset | |
3293 | set_isr_bit1 <= 1'b0 ; | |
3294 | end | |
3295 | end | |
3296 | wire isr_bit1 = set_isr_bit1 && !block_set_isr_bit1 ; | |
3297 | wire meta_isr_bit1 ; | |
3298 | // interemediate stage to clk synchronization flip - flops - this ones are prone to metastability | |
3299 | pci_synchronizer_flop #(1, 0) isr_bit1_sync | |
3300 | ( | |
3301 | .data_in (isr_bit1), | |
3302 | .clk_out (wb_clk), | |
3303 | .sync_data_out (meta_isr_bit1), | |
3304 | .async_reset (reset) | |
3305 | ) ; | |
3306 | always@(posedge wb_clk or posedge reset) | |
3307 | begin | |
3308 | if (reset) | |
3309 | isr_bit2_0[1] <= 1'b0 ; | |
3310 | else | |
3311 | isr_bit2_0[1] <= meta_isr_bit1 ; | |
3312 | end | |
3313 | // PCI_EINT STATUS BIT | |
3314 | // Set and clear FF | |
3315 | always@(posedge wb_clk or posedge reset) | |
3316 | begin | |
3317 | if (reset) // Asynchronous reset | |
3318 | isr_bit2_0[2] <= 1'b0 ; | |
3319 | else | |
3320 | begin | |
3321 | if (pci_error_sig && icr_bit2_0[2] && pci_err_cs_bit0) // Synchronous set | |
3322 | isr_bit2_0[2] <= 1'b1 ; | |
3323 | else if (delete_isr_bit2) // Synchronous reset | |
3324 | isr_bit2_0[2] <= 1'b0 ; | |
3325 | end | |
3326 | end | |
3327 | `else // GUEST | |
3328 | // WB_EINT STATUS BIT | |
3329 | // Set and clear FF | |
3330 | always@(posedge pci_clk or posedge reset) | |
3331 | begin | |
3332 | if (reset) // Asynchronous reset | |
3333 | isr_bit2_0[1] <= 1'b0 ; | |
3334 | else | |
3335 | begin | |
3336 | if (wb_error_sig && icr_bit2_0[1] && wb_err_cs_bit0) // Synchronous set | |
3337 | isr_bit2_0[1] <= 1'b1 ; | |
3338 | else if (delete_isr_bit1) // Synchronous reset | |
3339 | isr_bit2_0[1] <= 1'b0 ; | |
3340 | end | |
3341 | end | |
3342 | // PCI_EINT STATUS BIT | |
3343 | reg set_isr_bit2; | |
3344 | wire delete_set_isr_bit2; | |
3345 | wire block_set_isr_bit2; | |
3346 | // Synchronization module for clearing FF between two clock domains | |
3347 | pci_sync_module sync_isr_2 | |
3348 | ( | |
3349 | .set_clk_in (wb_clk), | |
3350 | .delete_clk_in (pci_clk), | |
3351 | .reset_in (reset), | |
3352 | .delete_set_out (delete_set_isr_bit2), | |
3353 | .block_set_out (block_set_isr_bit2), | |
3354 | .delete_in (delete_isr_bit2) | |
3355 | ); | |
3356 | // Setting FF | |
3357 | always@(posedge wb_clk or posedge reset) | |
3358 | begin | |
3359 | if (reset) // Asynchronous reset | |
3360 | set_isr_bit2 <= 1'b0 ; | |
3361 | else | |
3362 | begin | |
3363 | if (pci_error_sig && icr_bit2_0[2] && pci_err_cs_bit0) // Synchronous set | |
3364 | set_isr_bit2 <= 1'b1 ; | |
3365 | else if (delete_set_isr_bit2) // Synchronous reset | |
3366 | set_isr_bit2 <= 1'b0 ; | |
3367 | end | |
3368 | end | |
3369 | wire isr_bit2 = set_isr_bit2 && !block_set_isr_bit2 ; | |
3370 | wire meta_isr_bit2 ; | |
3371 | // interemediate stage to clk synchronization flip - flops - this ones are prone to metastability | |
3372 | pci_synchronizer_flop #(1, 0) isr_bit2_sync | |
3373 | ( | |
3374 | .data_in (isr_bit2), | |
3375 | .clk_out (pci_clk), | |
3376 | .sync_data_out (meta_isr_bit2), | |
3377 | .async_reset (reset) | |
3378 | ) ; | |
3379 | always@(posedge pci_clk or posedge reset) | |
3380 | begin | |
3381 | if (reset) | |
3382 | isr_bit2_0[2] <= 1'b0 ; | |
3383 | else | |
3384 | isr_bit2_0[2] <= meta_isr_bit2 ; | |
3385 | end | |
3386 | `endif | |
3387 | `endif | |
3388 | ||
3389 | // INT BIT of ISR - interrupt status register | |
3390 | `ifdef HOST | |
3391 | wire isr_int_prop_bit = isr_int_prop && icr_bit2_0[0] ; | |
3392 | wire meta_isr_int_prop_bit ; | |
3393 | // interemediate stage to clk synchronization flip - flops - this ones are prone to metastability | |
3394 | pci_synchronizer_flop #(1, 0) isr_bit0_sync | |
3395 | ( | |
3396 | .data_in (isr_int_prop_bit), | |
3397 | .clk_out (wb_clk), | |
3398 | .sync_data_out (meta_isr_int_prop_bit), | |
3399 | .async_reset (reset) | |
3400 | ) ; | |
3401 | always@(posedge wb_clk or posedge reset) | |
3402 | begin | |
3403 | if (reset) | |
3404 | isr_bit2_0[0] <= 1'b0 ; | |
3405 | else | |
3406 | isr_bit2_0[0] <= meta_isr_int_prop_bit ; | |
3407 | end | |
3408 | `else // GUEST | |
3409 | `ifdef SYNCHRONEOUS_CLOCK_DOMAINS | |
3410 | wire isr_int_prop_bit = isr_int_prop && icr_bit2_0[0] ; | |
3411 | always@(posedge pci_clk or posedge reset) | |
3412 | begin | |
3413 | if (reset) | |
3414 | isr_bit2_0[0] <= 1'b0 ; | |
3415 | else | |
3416 | isr_bit2_0[0] <= isr_int_prop_bit ; | |
3417 | end | |
3418 | `else // not SYNCHRONEOUS_CLOCK_DOMAINS | |
3419 | wire isr_int_prop_bit = isr_int_prop && icr_bit2_0[0] ; | |
3420 | wire meta_isr_int_prop_bit ; | |
3421 | // interemediate stage to clk synchronization flip - flops - this ones are prone to metastability | |
3422 | pci_synchronizer_flop #(1, 0) isr_bit0_sync | |
3423 | ( | |
3424 | .data_in (isr_int_prop_bit), | |
3425 | .clk_out (pci_clk), | |
3426 | .sync_data_out (meta_isr_int_prop_bit), | |
3427 | .async_reset (reset) | |
3428 | ) ; | |
3429 | always@(posedge pci_clk or posedge reset) | |
3430 | begin | |
3431 | if (reset) | |
3432 | isr_bit2_0[0] <= 1'b0 ; | |
3433 | else | |
3434 | isr_bit2_0[0] <= meta_isr_int_prop_bit ; | |
3435 | end | |
3436 | `endif | |
3437 | `endif | |
3438 | ||
3439 | // INT PIN | |
3440 | wire int_in; | |
3441 | wire int_meta; | |
3442 | reg interrupt_out; | |
3443 | `ifdef HOST | |
3444 | `ifdef SYNCHRONEOUS_CLOCK_DOMAINS | |
3445 | assign int_in = isr_int_prop_bit || isr_bit2_0[1] || isr_bit2_0[2] || isr_bit4_3[3] || isr_bit4_3[4]; | |
3446 | `else // not SYNCHRONEOUS_CLOCK_DOMAINS | |
3447 | assign int_in = isr_int_prop_bit || isr_bit1 || isr_bit2_0[2] || isr_bits4_3[3] || isr_bits4_3[4]; | |
3448 | `endif | |
3449 | // interemediate stage to clk synchronization flip - flops - this ones are prone to metastability | |
3450 | pci_synchronizer_flop #(1, 0) int_pin_sync | |
3451 | ( | |
3452 | .data_in (int_in), | |
3453 | .clk_out (wb_clk), | |
3454 | .sync_data_out (int_meta), | |
3455 | .async_reset (reset) | |
3456 | ) ; | |
3457 | always@(posedge wb_clk or posedge reset) | |
3458 | begin | |
3459 | if (reset) | |
3460 | interrupt_out <= 1'b0 ; | |
3461 | else | |
3462 | interrupt_out <= int_meta ; | |
3463 | end | |
3464 | `else // GUEST | |
3465 | `ifdef SYNCHRONEOUS_CLOCK_DOMAINS | |
3466 | assign int_in = isr_int_prop_bit || isr_bit2_0[1] || isr_bit2_0[2]; | |
3467 | `else // not SYNCHRONEOUS_CLOCK_DOMAINS | |
3468 | assign int_in = isr_int_prop_bit || isr_bit2_0[1] || isr_bit2; | |
3469 | `endif | |
3470 | // interemediate stage to clk synchronization flip - flops - this ones are prone to metastability | |
3471 | pci_synchronizer_flop #(1, 0) int_pin_sync | |
3472 | ( | |
3473 | .data_in (int_in), | |
3474 | .clk_out (pci_clk), | |
3475 | .sync_data_out (int_meta), | |
3476 | .async_reset (reset) | |
3477 | ) ; | |
3478 | always@(posedge pci_clk or posedge reset) | |
3479 | begin | |
3480 | if (reset) | |
3481 | interrupt_out <= 1'b0 ; | |
3482 | else | |
3483 | interrupt_out <= int_meta ; | |
3484 | end | |
3485 | `endif | |
3486 | ||
3487 | ||
3488 | `ifdef PCI_CPCI_HS_IMPLEMENT | |
3489 | reg [hs_es_cnt_width - 1:0] hs_es_cnt ; // debounce counter | |
3490 | reg hs_es_in_state, // current state of ejector switch input - synchronized | |
3491 | hs_es_sync, // synchronization flop for ejector switch input | |
3492 | hs_es_cur_state ; // current valid state of ejector switch | |
3493 | ||
3494 | `ifdef ACTIVE_HIGH_OE | |
3495 | wire oe_active_val = 1'b1 ; | |
3496 | `endif | |
3497 | ||
3498 | `ifdef ACTIVE_LOW_OE | |
3499 | wire oe_active_val = 1'b0 ; | |
3500 | `endif | |
3501 | ||
3502 | always@(posedge pci_clk or posedge reset) | |
3503 | begin | |
3504 | if (reset) | |
3505 | begin | |
3506 | hs_ins <= 1'b0 ; | |
3507 | hs_ins_armed <= 1'b1 ; | |
3508 | hs_ext <= 1'b0 ; | |
3509 | hs_ext_armed <= 1'b0 ; | |
3510 | hs_es_in_state <= 1'b0 ; | |
3511 | hs_es_sync <= 1'b0 ; | |
3512 | hs_es_cur_state <= 1'b0 ; | |
3513 | hs_es_cnt <= 'h0 ; | |
3514 | ||
3515 | `ifdef ACTIVE_LOW_OE | |
3516 | pci_cpci_hs_enum_oe_o <= 1'b1 ; | |
3517 | pci_cpci_hs_led_oe_o <= 1'b0 ; | |
3518 | `endif | |
3519 | ||
3520 | `ifdef ACTIVE_HIGH_OE | |
3521 | pci_cpci_hs_enum_oe_o <= 1'b0 ; | |
3522 | pci_cpci_hs_led_oe_o <= 1'b1 ; | |
3523 | `endif | |
3524 | ||
3525 | end | |
3526 | else | |
3527 | begin | |
3528 | // INS | |
3529 | if (hs_ins) | |
3530 | begin | |
3531 | if (w_conf_data[23] & ~w_byte_en[2] & w_we & w_reg_select_dec[56]) // clear | |
3532 | hs_ins <= 1'b0 ; | |
3533 | end | |
3534 | else if (hs_ins_armed) // set | |
3535 | hs_ins <= init_complete & (hs_es_cur_state == 1'b1) ; | |
3536 | ||
3537 | // INS armed | |
3538 | if (~hs_ins & hs_ins_armed & init_complete & (hs_es_cur_state == 1'b1)) // clear | |
3539 | hs_ins_armed <= 1'b0 ; | |
3540 | else if (hs_ext) // set | |
3541 | hs_ins_armed <= w_conf_data[22] & ~w_byte_en[2] & w_we & w_reg_select_dec[56] ; | |
3542 | ||
3543 | // EXT | |
3544 | if (hs_ext) // clear | |
3545 | begin | |
3546 | if (w_conf_data[22] & ~w_byte_en[2] & w_we & w_reg_select_dec[56]) | |
3547 | hs_ext <= 1'b0 ; | |
3548 | end | |
3549 | else if (hs_ext_armed) // set | |
3550 | hs_ext <= (hs_es_cur_state == 1'b0) ; | |
3551 | ||
3552 | // EXT armed | |
3553 | if (~hs_ext & hs_ext_armed & (hs_es_cur_state == 1'b0)) // clear | |
3554 | hs_ext_armed <= 1'b0 ; | |
3555 | else if (hs_ins) // set | |
3556 | hs_ext_armed <= w_conf_data[23] & !w_byte_en[2] & w_we & w_reg_select_dec[56] ; | |
3557 | ||
3558 | // ejector switch debounce counter logic | |
3559 | hs_es_sync <= pci_cpci_hs_es_i ; | |
3560 | hs_es_in_state <= hs_es_sync ; | |
3561 | ||
3562 | if (hs_es_in_state == hs_es_cur_state) | |
3563 | hs_es_cnt <= 'h0 ; | |
3564 | else | |
3565 | hs_es_cnt <= hs_es_cnt + 1'b1 ; | |
3566 | ||
3567 | if (hs_es_cnt == {hs_es_cnt_width{1'b1}}) | |
3568 | hs_es_cur_state <= hs_es_in_state ; | |
3569 | ||
3570 | if ((hs_ins | hs_ext) & ~hs_eim) | |
3571 | pci_cpci_hs_enum_oe_o <= oe_active_val ; | |
3572 | else | |
3573 | pci_cpci_hs_enum_oe_o <= ~oe_active_val ; | |
3574 | ||
3575 | if (~init_complete | hs_loo) | |
3576 | pci_cpci_hs_led_oe_o <= oe_active_val ; | |
3577 | else | |
3578 | pci_cpci_hs_led_oe_o <= ~oe_active_val ; | |
3579 | end | |
3580 | end | |
3581 | `endif | |
3582 | ||
3583 | `ifdef PCI_SPOCI | |
3584 | ||
3585 | wire spoci_write_done, | |
3586 | spoci_dat_rdy , | |
3587 | spoci_no_ack ; | |
3588 | ||
3589 | wire [ 7: 0] spoci_wdat ; | |
3590 | wire [ 7: 0] spoci_rdat ; | |
3591 | ||
3592 | // power on configuration control and status register | |
3593 | always@(posedge pci_clk or posedge reset) | |
3594 | begin | |
3595 | if (reset) | |
3596 | begin | |
3597 | spoci_cs_nack <= 1'b0 ; | |
3598 | spoci_cs_write <= 1'b0 ; | |
3599 | spoci_cs_read <= 1'b0 ; | |
3600 | spoci_cs_adr <= 'h0 ; | |
3601 | spoci_cs_dat <= 'h0 ; | |
3602 | end | |
3603 | else | |
3604 | begin | |
3605 | if (spoci_cs_write) | |
3606 | begin | |
3607 | if (spoci_write_done | spoci_no_ack) | |
3608 | spoci_cs_write <= 1'b0 ; | |
3609 | end | |
3610 | else if ( w_we & (w_conf_address[9:2] == 8'hFF) & ~w_byte_en[3]) | |
3611 | spoci_cs_write <= w_conf_data[25] ; | |
3612 | ||
3613 | if (spoci_cs_read) | |
3614 | begin | |
3615 | if (spoci_dat_rdy | spoci_no_ack) | |
3616 | spoci_cs_read <= 1'b0 ; | |
3617 | end | |
3618 | else if ( w_we & (w_conf_address[9:2] == 8'hFF) & ~w_byte_en[3] ) | |
3619 | spoci_cs_read <= w_conf_data[24] ; | |
3620 | ||
3621 | if (spoci_cs_nack) | |
3622 | begin | |
3623 | if ( w_we & (w_conf_address[9:2] == 8'hFF) & ~w_byte_en[3] & w_conf_data[31] ) | |
3624 | spoci_cs_nack <= 1'b0 ; | |
3625 | end | |
3626 | else if (spoci_cs_write | spoci_cs_read | ~init_cfg_done) | |
3627 | begin | |
3628 | spoci_cs_nack <= spoci_no_ack ; | |
3629 | end | |
3630 | ||
3631 | if ( w_we & (w_conf_address[9:2] == 8'hFF) ) | |
3632 | begin | |
3633 | if (~w_byte_en[2]) | |
3634 | spoci_cs_adr[10: 8] <= w_conf_data[18:16] ; | |
3635 | ||
3636 | if (~w_byte_en[1]) | |
3637 | spoci_cs_adr[ 7: 0] <= w_conf_data[15: 8] ; | |
3638 | end | |
3639 | ||
3640 | if ( w_we & (w_conf_address[9:2] == 8'hFF) & ~w_byte_en[0] ) | |
3641 | spoci_cs_dat <= w_conf_data[ 7: 0] ; | |
3642 | else if (spoci_cs_read & spoci_dat_rdy) | |
3643 | spoci_cs_dat <= spoci_rdat ; | |
3644 | ||
3645 | end | |
3646 | end | |
3647 | ||
3648 | reg [ 2 : 0] bytes_received ; | |
3649 | ||
3650 | always@(posedge pci_clk or posedge reset) | |
3651 | begin | |
3652 | if (reset) | |
3653 | begin | |
3654 | init_we <= 1'b0 ; | |
3655 | init_cfg_done <= 1'b0 ; | |
3656 | bytes_received <= 1'b0 ; | |
3657 | spoci_dat <= 'h0 ; | |
3658 | spoci_reg_num <= 'h0 ; | |
3659 | end | |
3660 | else if (~init_cfg_done) | |
3661 | begin | |
3662 | if (spoci_dat_rdy) | |
3663 | begin | |
3664 | case (bytes_received) | |
3665 | 'h0:spoci_reg_num <= spoci_rdat ; | |
3666 | 'h1:spoci_dat[ 7: 0] <= spoci_rdat ; | |
3667 | 'h2:spoci_dat[15: 8] <= spoci_rdat ; | |
3668 | 'h3:spoci_dat[23:16] <= spoci_rdat ; | |
3669 | 'h4:spoci_dat[31:24] <= spoci_rdat ; | |
3670 | default: | |
3671 | begin | |
3672 | spoci_dat <= 32'hxxxx_xxxx ; | |
3673 | spoci_reg_num <= 'hxx ; | |
3674 | end | |
3675 | endcase | |
3676 | end | |
3677 | ||
3678 | if (init_we) | |
3679 | bytes_received <= 'h0 ; | |
3680 | else if (spoci_dat_rdy) | |
3681 | bytes_received <= bytes_received + 1'b1 ; | |
3682 | ||
3683 | if (init_we) | |
3684 | init_we <= 1'b0 ; | |
3685 | else if (bytes_received == 'h5) | |
3686 | init_we <= 1'b1 ; | |
3687 | ||
3688 | if (spoci_no_ack | ((bytes_received == 'h1) & (spoci_reg_num == 'hff)) ) | |
3689 | init_cfg_done <= 1'b1 ; | |
3690 | end | |
3691 | end | |
3692 | ||
3693 | assign spoci_wdat = spoci_cs_dat ; | |
3694 | ||
3695 | pci_spoci_ctrl i_pci_spoci_ctrl | |
3696 | ( | |
3697 | .reset_i (reset ), | |
3698 | .clk_i (pci_clk ), | |
3699 | ||
3700 | .do_rnd_read_i (spoci_cs_read ), | |
3701 | .do_seq_read_i (rst_inactive & ~init_cfg_done ), | |
3702 | .do_write_i (spoci_cs_write ), | |
3703 | ||
3704 | .write_done_o (spoci_write_done ), | |
3705 | .dat_rdy_o (spoci_dat_rdy ), | |
3706 | .no_ack_o (spoci_no_ack ), | |
3707 | ||
3708 | .adr_i (spoci_cs_adr ), | |
3709 | .dat_i (spoci_wdat ), | |
3710 | .dat_o (spoci_rdat ), | |
3711 | ||
3712 | .pci_spoci_sda_i (spoci_sda_i ), | |
3713 | .pci_spoci_sda_oe_o (spoci_sda_oe_o ), | |
3714 | .pci_spoci_scl_oe_o (spoci_scl_oe_o ) | |
3715 | ); | |
3716 | `endif | |
3717 | ||
3718 | /*----------------------------------------------------------------------------------------------------------- | |
3719 | OUTPUTs from registers !!! | |
3720 | -----------------------------------------------------------------------------------------------------------*/ | |
3721 | ||
3722 | // if bridge is HOST then write clock is equal to WB clock, and synchronization of outputs has to be done | |
3723 | `ifdef HOST | |
3724 | wire [3:0] command_bits = {command_bit8, command_bit6, command_bit2_0[1:0]} ; | |
3725 | wire [3:0] meta_command_bits ; | |
3726 | reg [3:0] sync_command_bits ; | |
3727 | pci_synchronizer_flop #(4, 0) command_bits_sync | |
3728 | ( | |
3729 | .data_in (command_bits), | |
3730 | .clk_out (pci_clk), | |
3731 | .sync_data_out (meta_command_bits), | |
3732 | .async_reset (reset) | |
3733 | ) ; | |
3734 | always@(posedge pci_clk or posedge reset) | |
3735 | begin | |
3736 | if (reset) | |
3737 | sync_command_bits <= 4'b0 ; | |
3738 | else | |
3739 | sync_command_bits <= meta_command_bits ; | |
3740 | end | |
3741 | wire sync_command_bit8 = sync_command_bits[3] ; | |
3742 | wire sync_command_bit6 = sync_command_bits[2] ; | |
3743 | wire sync_command_bit1 = sync_command_bits[1] ; | |
3744 | wire sync_command_bit0 = sync_command_bits[0] ; | |
3745 | wire sync_command_bit2 = command_bit2_0[2] ; | |
3746 | `else // GUEST | |
3747 | wire command_bit = command_bit2_0[2] ; | |
3748 | wire meta_command_bit ; | |
3749 | reg sync_command_bit ; | |
3750 | pci_synchronizer_flop #(1, 0) command_bit_sync | |
3751 | ( | |
3752 | .data_in (command_bit), | |
3753 | .clk_out (pci_clk), | |
3754 | .sync_data_out (meta_command_bit), | |
3755 | .async_reset (reset) | |
3756 | ) ; | |
3757 | always@(posedge pci_clk or posedge reset) | |
3758 | begin | |
3759 | if (reset) | |
3760 | sync_command_bit <= 1'b0 ; | |
3761 | else | |
3762 | sync_command_bit <= meta_command_bit ; | |
3763 | end | |
3764 | wire sync_command_bit8 = command_bit8 ; | |
3765 | wire sync_command_bit6 = command_bit6 ; | |
3766 | wire sync_command_bit1 = command_bit2_0[1] ; | |
3767 | wire sync_command_bit0 = command_bit2_0[0] ; | |
3768 | wire sync_command_bit2 = sync_command_bit ; | |
3769 | `endif | |
3770 | // PCI header outputs from command register | |
3771 | assign serr_enable = sync_command_bit8 & pci_init_complete_out ; // to PCI clock | |
3772 | assign perr_response = sync_command_bit6 & pci_init_complete_out ; // to PCI clock | |
3773 | assign pci_master_enable = sync_command_bit2 & wb_init_complete_out ; // to WB clock | |
3774 | assign memory_space_enable = sync_command_bit1 & pci_init_complete_out ; // to PCI clock | |
3775 | assign io_space_enable = sync_command_bit0 & pci_init_complete_out ; // to PCI clock | |
3776 | ||
3777 | // if bridge is HOST then write clock is equal to WB clock, and synchronization of outputs has to be done | |
3778 | // We don't support cache line sizes smaller that 4 and it must have last two bits zero!!! | |
3779 | wire cache_lsize_not_zero = ((cache_line_size_reg[7] || cache_line_size_reg[6] || cache_line_size_reg[5] || | |
3780 | cache_line_size_reg[4] || cache_line_size_reg[3] || cache_line_size_reg[2]) && | |
3781 | (!cache_line_size_reg[1] && !cache_line_size_reg[0]) ); | |
3782 | `ifdef HOST | |
3783 | wire [7:2] cache_lsize_to_pci_bits = { cache_line_size_reg[7:2] } ; | |
3784 | wire [7:2] meta_cache_lsize_to_pci_bits ; | |
3785 | reg [7:2] sync_cache_lsize_to_pci_bits ; | |
3786 | pci_synchronizer_flop #(6, 0) cache_lsize_to_pci_bits_sync | |
3787 | ( | |
3788 | .data_in (cache_lsize_to_pci_bits), | |
3789 | .clk_out (pci_clk), | |
3790 | .sync_data_out (meta_cache_lsize_to_pci_bits), | |
3791 | .async_reset (reset) | |
3792 | ) ; | |
3793 | always@(posedge pci_clk or posedge reset) | |
3794 | begin | |
3795 | if (reset) | |
3796 | sync_cache_lsize_to_pci_bits <= 6'b0 ; | |
3797 | else | |
3798 | sync_cache_lsize_to_pci_bits <= meta_cache_lsize_to_pci_bits ; | |
3799 | end | |
3800 | wire [7:2] sync_cache_line_size_to_pci_reg = sync_cache_lsize_to_pci_bits[7:2] ; | |
3801 | wire [7:2] sync_cache_line_size_to_wb_reg = cache_line_size_reg[7:2] ; | |
3802 | wire sync_cache_lsize_not_zero_to_wb = cache_lsize_not_zero ; | |
3803 | // Latency timer is sinchronized only to PCI clock when bridge implementation is HOST | |
3804 | wire [7:0] latency_timer_bits = latency_timer ; | |
3805 | wire [7:0] meta_latency_timer_bits ; | |
3806 | reg [7:0] sync_latency_timer_bits ; | |
3807 | pci_synchronizer_flop #(8, 0) latency_timer_bits_sync | |
3808 | ( | |
3809 | .data_in (latency_timer_bits), | |
3810 | .clk_out (pci_clk), | |
3811 | .sync_data_out (meta_latency_timer_bits), | |
3812 | .async_reset (reset) | |
3813 | ) ; | |
3814 | always@(posedge pci_clk or posedge reset) | |
3815 | begin | |
3816 | if (reset) | |
3817 | sync_latency_timer_bits <= 8'b0 ; | |
3818 | else | |
3819 | sync_latency_timer_bits <= meta_latency_timer_bits ; | |
3820 | end | |
3821 | wire [7:0] sync_latency_timer = sync_latency_timer_bits ; | |
3822 | `else // GUEST | |
3823 | wire [8:2] cache_lsize_to_wb_bits = { cache_lsize_not_zero, cache_line_size_reg[7:2] } ; | |
3824 | wire [8:2] meta_cache_lsize_to_wb_bits ; | |
3825 | reg [8:2] sync_cache_lsize_to_wb_bits ; | |
3826 | pci_synchronizer_flop #(7, 0) cache_lsize_to_wb_bits_sync | |
3827 | ( | |
3828 | .data_in (cache_lsize_to_wb_bits), | |
3829 | .clk_out (wb_clk), | |
3830 | .sync_data_out (meta_cache_lsize_to_wb_bits), | |
3831 | .async_reset (reset) | |
3832 | ) ; | |
3833 | always@(posedge wb_clk or posedge reset) | |
3834 | begin | |
3835 | if (reset) | |
3836 | sync_cache_lsize_to_wb_bits <= 7'b0 ; | |
3837 | else | |
3838 | sync_cache_lsize_to_wb_bits <= meta_cache_lsize_to_wb_bits ; | |
3839 | end | |
3840 | wire [7:2] sync_cache_line_size_to_pci_reg = cache_line_size_reg[7:2] ; | |
3841 | wire [7:2] sync_cache_line_size_to_wb_reg = sync_cache_lsize_to_wb_bits[7:2] ; | |
3842 | wire sync_cache_lsize_not_zero_to_wb = sync_cache_lsize_to_wb_bits[8] ; | |
3843 | // Latency timer | |
3844 | wire [7:0] sync_latency_timer = latency_timer ; | |
3845 | `endif | |
3846 | // PCI header output from cache_line_size, latency timer and interrupt pin | |
3847 | assign cache_line_size_to_pci = {sync_cache_line_size_to_pci_reg, 2'h0} ; // [7 : 0] to PCI clock | |
3848 | assign cache_line_size_to_wb = {sync_cache_line_size_to_wb_reg, 2'h0} ; // [7 : 0] to WB clock | |
3849 | assign cache_lsize_not_zero_to_wb = sync_cache_lsize_not_zero_to_wb ; | |
3850 | ||
3851 | assign latency_tim[7 : 0] = sync_latency_timer ; // to PCI clock | |
3852 | //assign int_pin[2 : 0] = r_interrupt_pin ; | |
3853 | assign int_out = interrupt_out ; | |
3854 | // PCI output from image registers | |
3855 | // base address, address mask, translation address and control registers are sinchronized in PCI_DECODER.V module | |
3856 | `ifdef HOST | |
3857 | `ifdef NO_CNF_IMAGE | |
3858 | assign pci_base_addr0 = pci_ba0_bit31_8[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ; | |
3859 | `else | |
3860 | assign pci_base_addr0 = pci_ba0_bit31_8[31:12] ; | |
3861 | `endif | |
3862 | `endif | |
3863 | ||
3864 | `ifdef GUEST | |
3865 | assign pci_base_addr0 = pci_ba0_bit31_8[31:12] ; | |
3866 | `endif | |
3867 | ||
3868 | assign pci_base_addr1 = pci_ba1_bit31_8[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ; | |
3869 | assign pci_base_addr2 = pci_ba2_bit31_8[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ; | |
3870 | assign pci_base_addr3 = pci_ba3_bit31_8[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ; | |
3871 | assign pci_base_addr4 = pci_ba4_bit31_8[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ; | |
3872 | assign pci_base_addr5 = pci_ba5_bit31_8[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ; | |
3873 | assign pci_memory_io0 = pci_ba0_bit0 ; | |
3874 | assign pci_memory_io1 = pci_ba1_bit0 ; | |
3875 | assign pci_memory_io2 = pci_ba2_bit0 ; | |
3876 | assign pci_memory_io3 = pci_ba3_bit0 ; | |
3877 | assign pci_memory_io4 = pci_ba4_bit0 ; | |
3878 | assign pci_memory_io5 = pci_ba5_bit0 ; | |
3879 | ||
3880 | assign pci_addr_mask0 = pci_am0[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ; | |
3881 | assign pci_addr_mask1 = pci_am1[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ; | |
3882 | assign pci_addr_mask2 = pci_am2[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ; | |
3883 | assign pci_addr_mask3 = pci_am3[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ; | |
3884 | assign pci_addr_mask4 = pci_am4[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ; | |
3885 | assign pci_addr_mask5 = pci_am5[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ; | |
3886 | assign pci_tran_addr0 = pci_ta0[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ; | |
3887 | assign pci_tran_addr1 = pci_ta1[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ; | |
3888 | assign pci_tran_addr2 = pci_ta2[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ; | |
3889 | assign pci_tran_addr3 = pci_ta3[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ; | |
3890 | assign pci_tran_addr4 = pci_ta4[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ; | |
3891 | assign pci_tran_addr5 = pci_ta5[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ; | |
3892 | assign pci_img_ctrl0[2 : 1] = pci_img_ctrl0_bit2_1 ; | |
3893 | assign pci_img_ctrl1[2 : 1] = pci_img_ctrl1_bit2_1 ; | |
3894 | assign pci_img_ctrl2[2 : 1] = pci_img_ctrl2_bit2_1 ; | |
3895 | assign pci_img_ctrl3[2 : 1] = pci_img_ctrl3_bit2_1 ; | |
3896 | assign pci_img_ctrl4[2 : 1] = pci_img_ctrl4_bit2_1 ; | |
3897 | assign pci_img_ctrl5[2 : 1] = pci_img_ctrl5_bit2_1 ; | |
3898 | // WISHBONE output from image registers | |
3899 | // base address, address mask, translation address and control registers are sinchronized in DECODER.V module | |
3900 | assign wb_base_addr0 = wb_ba0_bit31_12[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] ; | |
3901 | assign wb_base_addr1 = wb_ba1_bit31_12[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] ; | |
3902 | assign wb_base_addr2 = wb_ba2_bit31_12[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] ; | |
3903 | assign wb_base_addr3 = wb_ba3_bit31_12[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] ; | |
3904 | assign wb_base_addr4 = wb_ba4_bit31_12[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] ; | |
3905 | assign wb_base_addr5 = wb_ba5_bit31_12[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] ; | |
3906 | assign wb_memory_io0 = wb_ba0_bit0 ; | |
3907 | assign wb_memory_io1 = wb_ba1_bit0 ; | |
3908 | assign wb_memory_io2 = wb_ba2_bit0 ; | |
3909 | assign wb_memory_io3 = wb_ba3_bit0 ; | |
3910 | assign wb_memory_io4 = wb_ba4_bit0 ; | |
3911 | assign wb_memory_io5 = wb_ba5_bit0 ; | |
3912 | assign wb_addr_mask0 = wb_am0[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] ; | |
3913 | assign wb_addr_mask1 = wb_am1[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] ; | |
3914 | assign wb_addr_mask2 = wb_am2[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] ; | |
3915 | assign wb_addr_mask3 = wb_am3[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] ; | |
3916 | assign wb_addr_mask4 = wb_am4[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] ; | |
3917 | assign wb_addr_mask5 = wb_am5[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] ; | |
3918 | assign wb_tran_addr0 = wb_ta0[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] ; | |
3919 | assign wb_tran_addr1 = wb_ta1[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] ; | |
3920 | assign wb_tran_addr2 = wb_ta2[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] ; | |
3921 | assign wb_tran_addr3 = wb_ta3[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] ; | |
3922 | assign wb_tran_addr4 = wb_ta4[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] ; | |
3923 | assign wb_tran_addr5 = wb_ta5[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] ; | |
3924 | assign wb_img_ctrl0[2 : 0] = wb_img_ctrl0_bit2_0 ; | |
3925 | assign wb_img_ctrl1[2 : 0] = wb_img_ctrl1_bit2_0 ; | |
3926 | assign wb_img_ctrl2[2 : 0] = wb_img_ctrl2_bit2_0 ; | |
3927 | assign wb_img_ctrl3[2 : 0] = wb_img_ctrl3_bit2_0 ; | |
3928 | assign wb_img_ctrl4[2 : 0] = wb_img_ctrl4_bit2_0 ; | |
3929 | assign wb_img_ctrl5[2 : 0] = wb_img_ctrl5_bit2_0 ; | |
3930 | // GENERAL output from conf. cycle generation register & int. control register | |
3931 | assign config_addr[23 : 0] = { cnf_addr_bit23_2, 1'b0, cnf_addr_bit0 } ; | |
3932 | assign icr_soft_res = icr_bit31 ; | |
3933 | ||
3934 | endmodule | |
3935 |